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* | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
* | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
* | Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2241-0/+8275
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* moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-251-10/+23
* bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
* pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
* more debug for fixing E'sMatt Ettus2010-03-101-5/+12
* better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
* Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-252-27/+26
* just debug pin changesMatt Ettus2010-01-251-1/+5
* moved into subdirJosh Blum2010-01-2241-0/+8358