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* proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
* ignoresMatt Ettus2010-06-081-0/+1
* debug pinsMatt Ettus2010-06-081-1/+2
* Merge branch 'master' into u1eMatt Ettus2010-06-082-2/+2
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| * report ise version in buildMatt Ettus2010-06-071-1/+1
| * proper name for directoryMatt Ettus2010-06-071-1/+1
| * name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
* | remove double declarationMatt Ettus2010-06-061-1/+1
* | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
* | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
* | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
* | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-014-160/+1218
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| * | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
| * | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual merg...Matt Ettus2010-05-282-30/+28
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| | * | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-261-15/+14
| * | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-284-15/+20
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| | * | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | * fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-2/+3
| | * removes the icache and pipelines the readsMatt Ettus2010-05-202-5/+6
| * | non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
| * | manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
| * | from UDP branch, changed names because I want these separate from the non-udp...Matt Ettus2010-05-272-0/+1138
| * | new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
| * | Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-271-1/+1
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* | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
* | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
* | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
* | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
* | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-272-8/+8
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| * | Merge branch 'master' into udpMatt Ettus2010-05-181-9/+9
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| * | ignoresMatt Ettus2010-05-181-1/+1
| * | Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
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| * | | move dsp settings regs to reclocked setting bus. Works, gets us to within 18...Matt Ettus2010-05-122-12/+19
| * | | Merge branch 'master' into udpMatt Ettus2010-05-111-1/+1
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| * \ \ \ Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-263-4/+15
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* | \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-2712-2089/+20
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| * | | | | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
| * | | | | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * | | | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
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* | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
* | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
* | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| * | | | better debug pinsMatt Ettus2010-05-171-6/+4
* | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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* | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
* | | | Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
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| * | | remove port which is no longer thereMatt Ettus2010-05-111-1/+1
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| * | Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
| * | Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
| * | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
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