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* assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
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* Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-272-8/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | * udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
| * Merge branch 'master' into udpMatt Ettus2010-05-181-9/+9
| |\ | | | | | | | | | | | | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | ignoresMatt Ettus2010-05-181-1/+1
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| * | Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
| |\ \ | | | | | | | | | | | | | | | | Conflicts: usrp2/control_lib/settings_bus.v
| * | | move dsp settings regs to reclocked setting bus. Works, gets us to within ↵Matt Ettus2010-05-122-12/+19
| | | | | | | | | | | | | | | | 18ps of passing timing
| * | | Merge branch 'master' into udpMatt Ettus2010-05-111-1/+1
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| * \ \ \ Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-263-4/+15
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* | \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-2712-2089/+20
|\ \ \ \ \ \ | | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * | | | | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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| * | | | | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * | | | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
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* | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
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* | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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* | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| * | | | better debug pinsMatt Ettus2010-05-171-6/+4
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* | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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* | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-122-22/+43
| | | | | | | | | | | | | | | | packet gen and test
* | | | Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
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| * | | remove port which is no longer thereMatt Ettus2010-05-111-1/+1
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| * | Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
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| * | Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
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| * | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
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| * | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs
* | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵Matt Ettus2010-05-108-561/+9
| | | | | | | | | | | | safe_u1e necessary.
* | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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* | | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
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* | | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
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* | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * | | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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* | | | changed commentMatt Ettus2010-05-041-1/+1
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* | | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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* | | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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* | | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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* | | find time_64bitMatt Ettus2010-04-201-0/+1
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* | | added pps and time capabilityMatt Ettus2010-04-153-5/+21
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* | | access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
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* | | async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-151-3/+3
| | | | | | | | | | | | for gpmc
* | | async gpmc progressMatt Ettus2010-04-152-18/+20
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* | | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
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* | | handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
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* | | more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
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* | | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
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* | | added in a loopback fifoMatt Ettus2010-04-141-4/+11
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* | | minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
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* | | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
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* | | added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| | | | | | | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* | | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
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* | | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | | | | | | | | | be read/controlled from SW
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