summaryrefslogtreecommitdiffstats
path: root/usrp2/top
Commit message (Expand)AuthorAgeFilesLines
* send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\
| * better debug pinsMatt Ettus2010-05-171-6/+4
* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
|/
* moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
* Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
|\
| * remove port which is no longer thereMatt Ettus2010-05-111-1/+1
| * Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
| * Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
| * Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
| * Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
* | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
* | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
* | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
* | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
* | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
|\ \
| * | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
* | | changed commentMatt Ettus2010-05-041-1/+1
|/ /
* | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
* | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
* | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
* | find time_64bitMatt Ettus2010-04-201-0/+1
* | added pps and time capabilityMatt Ettus2010-04-153-5/+21
* | access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
* | async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-151-3/+3
* | async gpmc progressMatt Ettus2010-04-152-18/+20
* | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
* | handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
* | more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
* | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
* | added in a loopback fifoMatt Ettus2010-04-141-4/+11
* | minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
* | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
* | added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
* | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
* | connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
* | Merge branch 'udp' into u1eMatt Ettus2010-03-252-57/+179
|\ \
| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-251-10/+23
| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
| * | more debug for fixing E'sMatt Ettus2010-03-101-5/+12
| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-252-27/+26
| * | just debug pin changesMatt Ettus2010-01-251-1/+5
| * | moved into subdirJosh Blum2010-01-2241-0/+8358
| /
* | connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
* | debug pinsMatt Ettus2010-02-251-2/+3
* | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
* | gpmc debug pinsMatt Ettus2010-02-251-3/+6
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-18 11:58:11 +0000