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* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\ | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| * better debug pinsMatt Ettus2010-05-171-6/+4
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* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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* moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-122-22/+43
| | | | packet gen and test
* Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
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| * remove port which is no longer thereMatt Ettus2010-05-111-1/+1
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| * Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
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| * Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
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| * Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
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| * Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs
* | switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵Matt Ettus2010-05-108-561/+9
| | | | | | | | safe_u1e necessary.
* | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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* | SPI passthru for programming clock gen chip on brand new boardsMatt Ettus2010-05-073-0/+391
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* | added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
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* | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * | add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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* | | changed commentMatt Ettus2010-05-041-1/+1
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* | separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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* | send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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* | Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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* | find time_64bitMatt Ettus2010-04-201-0/+1
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* | added pps and time capabilityMatt Ettus2010-04-153-5/+21
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* | access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
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* | async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-151-3/+3
| | | | | | | | for gpmc
* | async gpmc progressMatt Ettus2010-04-152-18/+20
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* | synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
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* | handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
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* | more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
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* | renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
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* | added in a loopback fifoMatt Ettus2010-04-141-4/+11
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* | minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
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* | replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
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* | added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| | | | | | | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* | connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
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* | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | | | | | be read/controlled from SW
* | Merge branch 'udp' into u1eMatt Ettus2010-03-252-57/+179
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| * | moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-251-10/+23
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| * | bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
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| * | pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
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| * | more debug for fixing E'sMatt Ettus2010-03-101-5/+12
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| * | better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-252-27/+26
| | | | | | | | | | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
| * | just debug pin changesMatt Ettus2010-01-251-1/+5
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| * | moved into subdirJosh Blum2010-01-2241-0/+8358
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* | connected spi pins, but the spi core still needs to be redone for 16 bit ↵Matt Ettus2010-03-253-40/+60
| | | | | | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
* | debug pinsMatt Ettus2010-02-251-2/+3
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* | invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
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* | gpmc debug pinsMatt Ettus2010-02-251-3/+6
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* | point to the new filesMatt Ettus2010-02-251-0/+2
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