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| * Merge branch 'tx_policy' into u1eMatt Ettus2010-08-252-7/+10
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| * | no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
| * | match the signal names in this designMatt Ettus2010-08-231-3/+3
| * | debug pins cleanupMatt Ettus2010-08-231-3/+3
| * | properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
| * | catch up with tx_policyMatt Ettus2010-08-192-30/+28
| * | attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
| * | connect atrMatt Ettus2010-08-171-1/+1
| * | delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
| * | this is necessary for some reasonMatt Ettus2010-08-131-1/+2
| * | connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
| * | enlarge loopback fifoMatt Ettus2010-08-101-4/+1
| * | Merge branch 'ise12' into u1eMatt Ettus2010-07-192-37/+36
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| * | | make loopback compileMatt Ettus2010-07-141-0/+3
| * | | Merge branch 'master' into u1eMatt Ettus2010-06-181-1/+2
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| * | | | added ability to clear out fifos of tx and rx.Matt Ettus2010-06-171-12/+21
| * | | | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-148-707/+216
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| * | | | | debug pinsMatt Ettus2010-06-101-3/+6
| * | | | | much bigger fifosMatt Ettus2010-06-101-2/+2
| * | | | | proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
| * | | | | ignoresMatt Ettus2010-06-081-0/+1
| * | | | | debug pinsMatt Ettus2010-06-081-1/+2
| * | | | | Merge branch 'master' into u1eMatt Ettus2010-06-082-2/+2
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| * | | | | | remove double declarationMatt Ettus2010-06-061-1/+1
| * | | | | | use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
| * | | | | | Phil wants gpio #145Matt Ettus2010-06-032-4/+4
| * | | | | | use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
| * | | | | | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-014-160/+1218
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| | * | | | | | zero out debug pins. helps timing a little bit.Matt Ettus2010-06-011-9/+11
| | * | | | | | Merge branch 'new_ramloader' into nocache_plus_newramloader, plus manual merg...Matt Ettus2010-05-282-30/+28
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| | | * | | | | | experimental mods to make ram loader fully synchronous. Based on IJB's workMatt Ettus2010-05-261-15/+14
| | * | | | | | | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-284-15/+20
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| | | * | | | | | | change the debug pins, which makes it more reliable. This is unnerving.Matt Ettus2010-05-261-1/+2
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| | | * | | | | | fixes from IJB from 5/24. Basically connect unconnected wires.Matt Ettus2010-05-241-2/+3
| | | * | | | | | removes the icache and pipelines the readsMatt Ettus2010-05-202-5/+6
| * | | | | | | | connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
| * | | | | | | | use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
| * | | | | | | | assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
| * | | | | | | | vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
| * | | | | | | | Merge branch 'udp' into u1e_merge_with_udpMatt Ettus2010-05-272-8/+8
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| * \ \ \ \ \ \ \ \ Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-2712-2089/+20
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| * | | | | | | | | send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
| * | | | | | | | | put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
| * | | | | | | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| | * | | | | | | | | better debug pinsMatt Ettus2010-05-171-6/+4
| * | | | | | | | | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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| * | | | | | | | | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
| * | | | | | | | | Merge branch 'master' into u1eMatt Ettus2010-05-124-5/+16
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| * | | | | | | | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-108-561/+9
| * | | | | | | | | | proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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