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* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
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* added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
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* connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | be read/controlled from SW
* Merge branch 'udp' into u1eMatt Ettus2010-03-252-57/+179
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| * moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-251-10/+23
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| * bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
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| * pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
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| * more debug for fixing E'sMatt Ettus2010-03-101-5/+12
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| * better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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| * Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-252-27/+26
| | | | | | | | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
| * just debug pin changesMatt Ettus2010-01-251-1/+5
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| * moved into subdirJosh Blum2010-01-2241-0/+8358
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* connected spi pins, but the spi core still needs to be redone for 16 bit ↵Matt Ettus2010-03-253-40/+60
| | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
* debug pinsMatt Ettus2010-02-251-2/+3
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* invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
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* gpmc debug pinsMatt Ettus2010-02-251-3/+6
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* point to the new filesMatt Ettus2010-02-251-0/+2
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* loopback and testMatt Ettus2010-02-251-2/+32
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* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-253-10/+24
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* first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+1
| | | | ISE chokes on the unequal size ram
* use our fancy new debug portsMatt Ettus2010-02-231-0/+3
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* settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-222-3/+14
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* GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
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* added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
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* Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
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* Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵Matt Ettus2010-02-182-4/+7
| | | | global set and reset module.
* wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-166-9/+49
| | | | timing and handle wait states.
* first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-165-34/+93
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* copied over from safe_u1eMatt Ettus2010-02-164-0/+553
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* block ram interface to GPMCMatt Ettus2010-02-161-2/+6
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* basic read support for the GPMC, responds with 16'hBEEFMatt Ettus2010-02-161-2/+8
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* reorg pin defsMatt Ettus2010-02-141-94/+102
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* connect GPMC pins to debug busMatt Ettus2010-02-142-76/+94
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* organized the pins in the ucf by functionMatt Ettus2010-02-091-56/+72
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* builds a successful led blinkerMatt Ettus2010-02-093-2/+4
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* first cut at blinking ledsMatt Ettus2010-02-094-345/+237
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* skeletons that don't work yetMatt Ettus2010-02-092-0/+607
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2241-0/+8275
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