uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	Merge branch 'master' into udp	Matt Ettus	2010-05-18	1	-9/+9
\|\ \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
\| *	get rid of some warnings by declaring setting reg width	Matt Ettus	2010-05-18	1	-8/+8
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\| *	settings bus to dsp_clk now uses clock crossing fifo	Matt Ettus	2010-05-16	2	-8/+15
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* \|	ignores	Matt Ettus	2010-05-18	1	-1/+1
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* \|	Merge branch 'master' into udp, removes u2_rev1, rev2	Matt Ettus	2010-05-13	10	-2076/+0
\|\\| \| \| \| \| \| \| \| \|	Conflicts: usrp2/control_lib/settings_bus.v
\| *	remove files for old prototypes, they were confusing people	Matt Ettus	2010-05-13	10	-2076/+0
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* \|	move dsp settings regs to reclocked setting bus. Works, gets us to within ↵	Matt Ettus	2010-05-12	2	-12/+19
\| \| \| \| \| \| \| \|	18ps of passing timing
* \|	Merge branch 'master' into udp	Matt Ettus	2010-05-11	1	-1/+1
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\| *	remove port which is no longer there	Matt Ettus	2010-05-11	1	-1/+1
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* \|	Merge branch 'corgan_fixes' into udp_corgan	Matt Ettus	2010-04-26	3	-4/+15
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\| *	Update config to all eight clock buffers to be used.	Johnathan Corgan	2010-03-29	1	-1/+1
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\| *	Added timing constraint for Wishbone clock/dsp_clock skew	Johnathan Corgan	2010-03-29	1	-0/+2
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\| *	Cut debug bus connection to etherenet MAC to make closing timing easier	Ian Buckley	2010-02-24	1	-2/+7
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\| *	Manually assign clk_fpga to BUFG to improve timing	Johnathan Corgan	2010-02-23	1	-1/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs
\| *	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	41	-0/+8275
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*	moved fifos around, now easier to see where they are and how big	Matt Ettus	2010-03-25	1	-10/+23
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*	bigger fifo on UDP TX path, to possibly fix overruns on decim=4	Matt Ettus	2010-03-24	1	-2/+11
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*	pps and vita time debug pins	Matt Ettus	2010-03-23	1	-3/+6
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*	more debug for fixing E's	Matt Ettus	2010-03-10	1	-5/+12
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*	better debug pins for going after cascading E's	Matt Ettus	2010-03-10	1	-1/+5
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*	Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp	Matt Ettus	2010-01-25	2	-27/+26
\| \| \| \| \| \| \| \|	Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
*	just debug pin changes	Matt Ettus	2010-01-25	1	-1/+5
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*	moved into subdir	Josh Blum	2010-01-22	41	-0/+8358