summaryrefslogtreecommitdiffstats
path: root/usrp2/top
Commit message (Collapse)AuthorAgeFilesLines
* Merge branch 'cordic_policy' into nextJosh Blum2011-01-042-31/+23
|\ | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v usrp2/top/u2plus/u2plus_core.v
| * hook up sampled pps in u2plus, remove unused priority encoder, minor cleanupsMatt Ettus2010-12-302-26/+18
| |
| * processor can read back vita_time at last ppsMatt Ettus2010-12-301-10/+4
| |
* | usrp-n210: checked in updated bootloader (from next with fixes)Josh Blum2010-12-311-36/+36
| |
* | Merge branch 'udp_ports' into nextJosh Blum2010-12-222-2/+4
|\ \
| * | generate port number headers in the dsp error unitsMatt Ettus2010-12-152-2/+4
| |/
* | usrp-n210: add missing wires, incr compat, use boot ram as stack spaceJosh Blum2010-12-221-16/+14
| |
* | usrp-n210: delay reset for boot loader stack pointer to init, copied bl.rmi ↵Josh Blum2010-12-182-187/+173
| | | | | | | | without debug
* | usrp-n210: almost working w/ packet router + zpuJosh Blum2010-12-173-293/+305
| | | | | | | | | | | | | | added stack start signal to zpu removed wb perifs in n210 out of 0-16k added reset controller for main app rewire cpu addr line after booted use 0-16k
* | usrp-n210: integrate zpu and packet router, builds but untestedJosh Blum2010-12-141-72/+77
| |
* | zpu: working, modified top level sizes, disable interruptJosh Blum2010-12-142-8/+5
| |
* | Merge branch 'packet_router' into zpuJosh Blum2010-12-128-128/+36
|\ \ | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v
| * | Merge branch 'ise12' into packet_routerJosh Blum2010-12-107-30/+34
| |\| | | | | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/u2_core.v
| | * time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-101-1/+5
| | |
| | * Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-091-0/+0
| | |
| | * udp is now the defaultMatt Ettus2010-12-092-2/+2
| | |
| | * remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
| | |
| | * reimplemented mimo time transfer to handle 64 bits. Still needsMatt Ettus2010-12-091-1/+2
| | | | | | | | | | | | to sync on the received side.
| | * renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-095-22/+22
| | |
| | * u2plus: clock lock pin capitalization failNick Foster2010-12-062-2/+2
| | |
| * | packet_router: renamed top level files in an attempt to merge cleanlyJosh Blum2010-12-104-1091/+209
| | |
* | | zpu: moved top level file in hopes for easy mergeJosh Blum2010-12-122-1014/+229
| | |
* | | zpu: moved stack pointer and made connection for statusJosh Blum2010-12-061-1/+2
| | |
* | | zpu: shrank the ram size and address bus to 16kJosh Blum2010-12-061-5/+5
| | |
* | | zpu: added a zpu + wishbone opencore and integrated into top levelJosh Blum2010-12-061-10/+18
|/ /
* | packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-1/+1
| |
* | packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-1/+1
| |
* | packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-231-16/+27
| | | | | | | | udp_wrapper in top level with some fifo conversion stuff
* | packet_router: implemented crossbar and valve module, moved sreg into router ↵Josh Blum2010-11-231-16/+7
| | | | | | | | module
* | packet_router: transplanted the async error interface, its now sent into the ↵Josh Blum2010-11-231-10/+5
| | | | | | | | packet router to be muxed to com out
* | packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-1/+3
| |
* | packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-2/+4
| |
* | packet_router: removed unused status words from readback muxJosh Blum2010-11-231-3/+3
| |
* | packet_router: fixed swapped connection typo, dsp tx routing worksJosh Blum2010-11-231-2/+3
| |
* | packet_router: added all input/output signals to module, created the comm ↵Josh Blum2010-11-231-0/+3
| | | | | | | | muxes (in and out)
* | packet_router: created inspector and added dsp output (however inspection ↵Josh Blum2010-11-231-0/+1
| | | | | | | | logic does not enable it yet)
* | packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-231-19/+14
|/
* shouldn't be executableMatt Ettus2010-11-201-0/+0
|
* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
|
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-111-11/+12
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-111-3/+9
| | | | style fifo in rx.
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
|
* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
|
* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-111-1/+2
| | | | without flow control
* Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵Ian Buckley2010-11-111-49/+4
| | | | | | u2plus. Hardcoded -90 degree clcok from first DCM as final solution
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-112-2/+5
| | | | | | | | | | | | | | | which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.
* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
|
* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
| | | | | Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals.
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-114-7/+123
| | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-32/+32
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 11:25:45 +0000