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* | zpu: working, modified top level sizes, disable interruptJosh Blum2010-12-142-8/+5
* | Merge branch 'packet_router' into zpuJosh Blum2010-12-128-128/+36
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| * | Merge branch 'ise12' into packet_routerJosh Blum2010-12-107-30/+34
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| | * time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-101-1/+5
| | * Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-091-0/+0
| | * udp is now the defaultMatt Ettus2010-12-092-2/+2
| | * remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
| | * reimplemented mimo time transfer to handle 64 bits. Still needsMatt Ettus2010-12-091-1/+2
| | * renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-095-22/+22
| | * u2plus: clock lock pin capitalization failNick Foster2010-12-062-2/+2
| * | packet_router: renamed top level files in an attempt to merge cleanlyJosh Blum2010-12-104-1091/+209
* | | zpu: moved top level file in hopes for easy mergeJosh Blum2010-12-122-1014/+229
* | | zpu: moved stack pointer and made connection for statusJosh Blum2010-12-061-1/+2
* | | zpu: shrank the ram size and address bus to 16kJosh Blum2010-12-061-5/+5
* | | zpu: added a zpu + wishbone opencore and integrated into top levelJosh Blum2010-12-061-10/+18
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* | packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-1/+1
* | packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-1/+1
* | packet_router: moved udp tx proto machine into packet router, replaced udp_wr...Josh Blum2010-11-231-16/+27
* | packet_router: implemented crossbar and valve module, moved sreg into router ...Josh Blum2010-11-231-16/+7
* | packet_router: transplanted the async error interface, its now sent into the ...Josh Blum2010-11-231-10/+5
* | packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-1/+3
* | packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-2/+4
* | packet_router: removed unused status words from readback muxJosh Blum2010-11-231-3/+3
* | packet_router: fixed swapped connection typo, dsp tx routing worksJosh Blum2010-11-231-2/+3
* | packet_router: added all input/output signals to module, created the comm mux...Josh Blum2010-11-231-0/+3
* | packet_router: created inspector and added dsp output (however inspection log...Josh Blum2010-11-231-0/+1
* | packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-231-19/+14
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* shouldn't be executableMatt Ettus2010-11-201-0/+0
* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-111-11/+12
* added ability to truly clear out the entire rx chain. also removed old style...Matt Ettus2010-11-111-3/+9
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-11-111-1/+2
* Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2pl...Ian Buckley2010-11-111-49/+4
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-112-2/+5
* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-114-7/+123
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-32/+32
* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
* Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-11-111-1/+1
* Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-11-111-12/+12
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-11-114-5/+100
* hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
* Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-11-112-37/+42
* Added a bunch of debug signals.Ian Buckley2010-11-111-4/+5
* Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-11-111-1/+2
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-11-115-142/+201
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1019-0/+1381
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