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* time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-101-1/+5
* Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-091-0/+0
* udp is now the defaultMatt Ettus2010-12-092-2/+2
* remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
* reimplemented mimo time transfer to handle 64 bits. Still needsMatt Ettus2010-12-091-1/+2
* renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-095-22/+22
* u2plus: clock lock pin capitalization failNick Foster2010-12-062-2/+2
* shouldn't be executableMatt Ettus2010-11-201-0/+0
* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-112-34/+38
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-111-11/+12
* added ability to truly clear out the entire rx chain. also removed old style...Matt Ettus2010-11-111-3/+9
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
* separated flow control and error reporting on tx path. should work with and ...Matt Ettus2010-11-111-1/+2
* Removed 'ifdef for second DCM that was a deign idea for external SRAM on u2pl...Ian Buckley2010-11-111-49/+4
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-112-2/+5
* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-114-7/+123
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-32/+32
* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
* Modified phase shift of DCM1 to -64 which is intended to give more timing mar...Ian Buckley2010-11-111-1/+1
* Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S...Ian Buckley2010-11-111-12/+12
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i...Ian Buckley2010-11-114-5/+100
* hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
* Corrected extfifo code so that all registers that are on SRAM signals are pac...ianb2010-11-112-37/+42
* Added a bunch of debug signals.Ian Buckley2010-11-111-4/+5
* Regenerated FIFO with lower trigger level for almost full flag to reflect log...Ian Buckley2010-11-111-1/+2
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu...Ian Buckley2010-11-115-142/+201
* Merge branch 'u1e' into merge_u1eMatt Ettus2010-11-1019-0/+1381
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| * invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
| * duhMatt Ettus2010-11-041-1/+1
| * better debug pinsMatt Ettus2010-09-232-7/+11
| * watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
| * fix timing issue on DAC outputs with rev 2. This puts the whole system on a ...Matt Ettus2010-09-212-50/+25
| * send all gpmc signals to mictorMatt Ettus2010-09-164-0/+201
| * updated pins to match rev2, removed dip switch, etc. seems to compile ok.Matt Ettus2010-09-093-137/+130
| * pins are different on rev2Matt Ettus2010-09-091-264/+4
| * fixed makefile to compile with our new systemMatt Ettus2010-09-071-44/+36
| * add register to tell host about compatibility level and which image we are usingMatt Ettus2010-08-301-5/+14
| * move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
| * Merge branch 'tx_policy' into u1eMatt Ettus2010-08-252-7/+10
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| * | no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
| * | match the signal names in this designMatt Ettus2010-08-231-3/+3
| * | debug pins cleanupMatt Ettus2010-08-231-3/+3
| * | properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
| * | catch up with tx_policyMatt Ettus2010-08-192-30/+28
| * | attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
| * | connect atrMatt Ettus2010-08-171-1/+1
| * | delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
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