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* Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-08-191-1/+2
| | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-07-315-140/+227
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* Merge branch 'master' into ise12Matt Ettus2010-06-181-1/+2
|\ | | | | | | | | * master: proper dependency tracking for the makefile
| * proper dependency tracking for the makefileMatt Ettus2010-06-181-1/+2
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* | barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but allMatt Ettus2010-06-142-52/+51
|/ | | | seem to work ok
* new make works on ise12Matt Ettus2010-06-141-1/+7
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* produces good bin filesMatt Ettus2010-06-114-57/+31
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* first attempt at cleaning up the build systemMatt Ettus2010-06-104-414/+149
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* get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
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* move u2_core into u2_rev3 directory to simplify directory structure and save ↵Matt Ettus2010-06-085-46/+2
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* report ise version in buildMatt Ettus2010-06-071-1/+1
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* proper name for directoryMatt Ettus2010-06-071-1/+1
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* name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
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* non-udp uses a different address for the tx dsp coreMatt Ettus2010-05-271-1/+1
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* manual merge to use localparams from udp versionMatt Ettus2010-05-271-4/+23
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* from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-272-0/+1138
| | | | non-udp versions
* new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
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* Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-271-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
| * Merge branch 'master' into udpMatt Ettus2010-05-181-9/+9
| |\ | |/ |/| | | | | | | | | | | Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
* | get rid of some warnings by declaring setting reg widthMatt Ettus2010-05-181-8/+8
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* | settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-162-8/+15
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| * ignoresMatt Ettus2010-05-181-1/+1
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| * Merge branch 'master' into udp, removes u2_rev1, rev2Matt Ettus2010-05-1310-2076/+0
| |\ | |/ |/| | | | | Conflicts: usrp2/control_lib/settings_bus.v
* | remove files for old prototypes, they were confusing peopleMatt Ettus2010-05-1310-2076/+0
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| * move dsp settings regs to reclocked setting bus. Works, gets us to within ↵Matt Ettus2010-05-122-12/+19
| | | | | | | | 18ps of passing timing
| * Merge branch 'master' into udpMatt Ettus2010-05-111-1/+1
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* | remove port which is no longer thereMatt Ettus2010-05-111-1/+1
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| * Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-263-4/+15
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* | Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
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* | Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
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* | Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
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* | Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs
* | Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-2241-0/+8275
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* moved fifos around, now easier to see where they are and how bigMatt Ettus2010-03-251-10/+23
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* bigger fifo on UDP TX path, to possibly fix overruns on decim=4Matt Ettus2010-03-241-2/+11
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* pps and vita time debug pinsMatt Ettus2010-03-231-3/+6
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* more debug for fixing E'sMatt Ettus2010-03-101-5/+12
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* better debug pins for going after cascading E'sMatt Ettus2010-03-101-1/+5
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* Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-252-27/+26
| | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v
* just debug pin changesMatt Ettus2010-01-251-1/+5
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* moved into subdirJosh Blum2010-01-2241-0/+8358
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