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* u2plus: clock lock pin capitalization failNick Foster2010-12-062-2/+2
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* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-111-30/+37
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* Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵Ian Buckley2010-11-111-49/+4
| | | | | | u2plus. Hardcoded -90 degree clcok from first DCM as final solution
* 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZIan Buckley2010-11-112-2/+5
| | | | | | | | | | | | | | | which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles.
* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
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* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-112-7/+23
| | | | | Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals.
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-114-7/+123
| | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
* remove old commented out codeMatt Ettus2010-11-091-4/+2
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* U2P: Working ICAP bootloader. Should be ready for release.Nick Foster2010-10-081-224/+236
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* U2P: modified ICAP. turns out ICAP needs clock disabled while CE is not ↵Nick Foster2010-10-071-199/+228
| | | | | | asserted. which is the point of a CE, but... it works. Also committed latest bootloader, might not be final version.
* separate the bootloader image into another fileMatt Ettus2010-10-072-204/+205
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* U2P: newest bootloader with support for 32Mbit flashNick Foster2010-10-051-157/+196
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* Fixed PPS. Instantiation was miscapitalized.Nick Foster2010-08-271-1/+1
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* invert adc_a because it is inverted on schematic. Also clean up extraneousMatt Ettus2010-08-251-15/+18
| | | | adc signals from old adc on U2
* SWAP DAC A and B, invert B to match schematicsMatt Ettus2010-08-251-3/+4
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* Use new tx_policy stuff, reassigned leds to be just like U2Matt Ettus2010-08-252-36/+34
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* Added a sanity checker Python script.Nick Foster2010-08-242-2/+2
| | | | | | The script just looks for input/inout/outputs that are declared in the .v but not in the .ucf. If it finds an occurrence, it aborts the compile. Removed pin "POR" from u2plus.v due to the script. Also reverted an error I introduced to test the script, which I mistakenly committed earlier.
* Ensure ethernet LED pin has 12mA outputNick Foster2010-08-241-1/+1
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* Added 12mA current spec to eth phy LED pin.Nick Foster2010-08-202-2/+3
| | | | Changed debug pins to debug ICAP instead of VITA -- which makes it actually meet timing, too. Bonus.
* Fixed u2plus_core.v to use quad_uart instead of simple_uart.Nick Foster2010-08-121-1/+1
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* quad uart instead of single, for the extra on board serial portsMatt Ettus2010-08-112-10/+10
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* Added DCM reset line to sr.Nick Foster2010-07-291-3/+5
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* latest bootloader in core, fixed eth_led to be active high, connected eth clkNick Foster2010-07-282-39/+167
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* Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2pNick Foster2010-07-271-0/+4
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| * capitalization matchingMatt Ettus2010-07-211-1/+5
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* | fix timing races on ADC and DAC pinsNick Foster2010-07-271-10/+20
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* reconnect the serial clockMatt Ettus2010-07-201-1/+1
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* connect SPI to adc, correct capitalization of SEN pinsMatt Ettus2010-07-202-9/+11
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* Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2pNick Foster2010-07-192-2/+4
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| * pushbutton now goes into interrupt controller, can be read from software. ↵Matt Ettus2010-07-192-2/+4
| | | | | | | | Normally high, goes low when pushed
* | Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2pNick Foster2010-07-141-1/+1
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| * reset the ack signalMatt Ettus2010-07-131-1/+1
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* | just local commit before updating w/matt's fixnick2010-07-141-5/+45
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* includes led blinker in bootramMatt Ettus2010-07-131-3/+7
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* separate boot ram, redone memory map, connected uartMatt Ettus2010-07-132-38/+40
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* further cleanupMatt Ettus2010-07-122-216/+27
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* remove ram loaderMatt Ettus2010-07-121-29/+8
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* updated to ise12 fixes from main development lineMatt Ettus2010-07-121-22/+22
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* new core for u2p, based on u2_coreMatt Ettus2010-06-141-0/+856
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* build using new build systemMatt Ettus2010-06-141-205/+34
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* actually generates an imageMatt Ettus2010-06-093-17/+9
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* compiles now, added clock constraintsMatt Ettus2010-06-072-3/+43
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* skeleton files copied over from a dead branchMatt Ettus2010-06-075-374/+717
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-222-0/+731
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