| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | first cut at using lvds for adc pins | Matt Ettus | 2011-06-07 | 1 | -0/+1 |
| | | |||||
| * | N210: how the heck did the PPS fix get dropped again | Nick Foster | 2011-05-20 | 1 | -1/+4 |
| | | |||||
| * | renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signal | Matt Ettus | 2010-12-09 | 1 | -2/+2 |
| | | |||||
| * | u2plus: clock lock pin capitalization fail | Nick Foster | 2010-12-06 | 1 | -1/+1 |
| | | |||||
| * | Removed 'ifdef for second DCM that was a deign idea for external SRAM on ↵ | Ian Buckley | 2010-11-11 | 1 | -49/+4 |
| | | | | | | | u2plus. Hardcoded -90 degree clcok from first DCM as final solution | ||||
| * | 1) u2p has added a new signal from the SRAM to the pinout, RAM_ZZ | Ian Buckley | 2010-11-11 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | which allows the SRAM to be placed in a sleep mode. This pin was erroniously pulled high at the top level rendering the SRAM unusable. 2) Added declaration for extramfifo debug bus which had got deleted at some point in the past 3) Created a debug bundle of signals from extsramfifo to help diagnose problem 1) 4) u2p Rev1 PCB ommits control of any of the SRAM chip selects. Made a code change so that control logic does not rely on the presence of this pin and ensuring that the SRAM is always placed in READ mode in any idle cycles. | ||||
| * | Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by default | Ian Buckley | 2010-11-11 | 1 | -3/+19 |
| | | | | | | Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals. | ||||
| * | Added external RAM FIFO to u2plus. | Ian Buckley | 2010-11-11 | 1 | -4/+79 |
| | | | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3 | ||||
| * | Fixed PPS. Instantiation was miscapitalized. | Nick Foster | 2010-08-27 | 1 | -1/+1 |
| | | |||||
| * | invert adc_a because it is inverted on schematic. Also clean up extraneous | Matt Ettus | 2010-08-25 | 1 | -15/+18 |
| | | | | | adc signals from old adc on U2 | ||||
| * | SWAP DAC A and B, invert B to match schematics | Matt Ettus | 2010-08-25 | 1 | -3/+4 |
| | | |||||
| * | Use new tx_policy stuff, reassigned leds to be just like U2 | Matt Ettus | 2010-08-25 | 1 | -1/+1 |
| | | |||||
| * | Added a sanity checker Python script. | Nick Foster | 2010-08-24 | 1 | -1/+1 |
| | | | | | | | The script just looks for input/inout/outputs that are declared in the .v but not in the .ucf. If it finds an occurrence, it aborts the compile. Removed pin "POR" from u2plus.v due to the script. Also reverted an error I introduced to test the script, which I mistakenly committed earlier. | ||||
| * | quad uart instead of single, for the extra on board serial ports | Matt Ettus | 2010-08-11 | 1 | -3/+2 |
| | | |||||
| * | Added DCM reset line to sr. | Nick Foster | 2010-07-29 | 1 | -3/+5 |
| | | |||||
| * | latest bootloader in core, fixed eth_led to be active high, connected eth clk | Nick Foster | 2010-07-28 | 1 | -2/+2 |
| | | |||||
| * | Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2p | Nick Foster | 2010-07-27 | 1 | -0/+4 |
| |\ | |||||
| | * | capitalization matching | Matt Ettus | 2010-07-21 | 1 | -1/+5 |
| | | | |||||
| * | | fix timing races on ADC and DAC pins | Nick Foster | 2010-07-27 | 1 | -10/+20 |
| |/ | |||||
| * | reconnect the serial clock | Matt Ettus | 2010-07-20 | 1 | -1/+1 |
| | | |||||
| * | connect SPI to adc, correct capitalization of SEN pins | Matt Ettus | 2010-07-20 | 1 | -8/+9 |
| | | |||||
| * | pushbutton now goes into interrupt controller, can be read from software. ↵ | Matt Ettus | 2010-07-19 | 1 | -0/+1 |
| | | | | | Normally high, goes low when pushed | ||||
| * | separate boot ram, redone memory map, connected uart | Matt Ettus | 2010-07-13 | 1 | -3/+3 |
| | | |||||
| * | further cleanup | Matt Ettus | 2010-07-12 | 1 | -3/+3 |
| | | |||||
| * | actually generates an image | Matt Ettus | 2010-06-09 | 1 | -11/+6 |
| | | |||||
| * | skeleton files copied over from a dead branch | Matt Ettus | 2010-06-07 | 1 | -132/+142 |
| | | |||||
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 1 | -0/+377 |
 |
index : uhd | |
| Ettus' UHD Repository |
| aboutsummaryrefslogtreecommitdiffstats |