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path: root/usrp2/top/u2plus/u2plus.ucf
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* Defaulted all SRAM pins to LVCMOS25 8mA FASTIan Buckley2010-11-111-67/+67
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* Placed 2nd DCM into `ifdef DCM_FOR_RAMCLK which is dissabled by defaultIan Buckley2010-11-111-4/+4
| | | | | Derived RAMCLK from 270degree offset of principle core DCM giving theoretical 2.5nS timing advance on RAM_CLK relative to RAM_* signals.
* Added external RAM FIFO to u2plus.Ian Buckley2010-11-111-0/+8
| | | | | | | | | | Added code branch to ext_fifo.v using generate that instantiates different input and out fifo's and touched nobl_fifo code so that it works at 18 and 36bit widths. Added 2nd DCM to top level to generate off chip RAMCLK. Added explicit I/O instances to top level for tristate drivers and changed signals to core as needed. Creted new FIFO's in core gen to replace much larger FIFO's used on u2rev3
* Added a sanity checker Python script.Nick Foster2010-08-241-1/+1
| | | | | | The script just looks for input/inout/outputs that are declared in the .v but not in the .ucf. If it finds an occurrence, it aborts the compile. Removed pin "POR" from u2plus.v due to the script. Also reverted an error I introduced to test the script, which I mistakenly committed earlier.
* Ensure ethernet LED pin has 12mA outputNick Foster2010-08-241-1/+1
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* Added 12mA current spec to eth phy LED pin.Nick Foster2010-08-201-1/+1
| | | | Changed debug pins to debug ICAP instead of VITA -- which makes it actually meet timing, too. Bonus.
* actually generates an imageMatt Ettus2010-06-091-3/+0
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* compiles now, added clock constraintsMatt Ettus2010-06-071-0/+18
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* skeleton files copied over from a dead branchMatt Ettus2010-06-071-242/+289
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-221-0/+354
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