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* u2/u2p: reduce unneeded RX DSP bufferingMatt Ettus2011-02-171-1/+1
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* u2/u2p: added 2nd DSP unitMatt Ettus2011-02-171-0/+34
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* u2/u2p: renamed and split some rx signals to prepare for 2nd DSPMatt Ettus2011-02-171-25/+22
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* u2/u2p: proper hookup of vita_rx_chainMatt Ettus2011-02-171-5/+5
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* clean up rx dsp and some other nets in prep for dual dspMatt Ettus2011-02-161-34/+21
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* register map changes to fit in the 2nd rx dspMatt Ettus2011-02-151-15/+19
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* packet_router: added support for two dsps into routerJosh Blum2011-02-151-1/+2
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* Merge branch 'cordic_policy' into nextJosh Blum2011-01-041-20/+15
|\ | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v usrp2/top/u2plus/u2plus_core.v
| * hook up sampled pps in u2plus, remove unused priority encoder, minor cleanupsMatt Ettus2010-12-301-12/+10
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| * processor can read back vita_time at last ppsMatt Ettus2010-12-301-10/+4
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* | Merge branch 'udp_ports' into nextJosh Blum2010-12-221-1/+2
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| * | generate port number headers in the dsp error unitsMatt Ettus2010-12-151-1/+2
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* | usrp-n210: almost working w/ packet router + zpuJosh Blum2010-12-171-13/+3
| | | | | | | | | | | | | | added stack start signal to zpu removed wb perifs in n210 out of 0-16k added reset controller for main app rewire cpu addr line after booted use 0-16k
* | zpu: working, modified top level sizes, disable interruptJosh Blum2010-12-142-8/+5
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* | Merge branch 'packet_router' into zpuJosh Blum2010-12-125-121/+28
|\ \ | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v
| * | Merge branch 'ise12' into packet_routerJosh Blum2010-12-104-23/+26
| |\| | | | | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/u2_core.v
| | * time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-101-1/+5
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| | * Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-091-0/+0
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| | * udp is now the defaultMatt Ettus2010-12-092-2/+2
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| | * remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
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| | * renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-093-18/+18
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| * | packet_router: renamed top level files in an attempt to merge cleanlyJosh Blum2010-12-104-1091/+209
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* | | zpu: moved top level file in hopes for easy mergeJosh Blum2010-12-122-1014/+229
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* | | zpu: moved stack pointer and made connection for statusJosh Blum2010-12-061-1/+2
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* | | zpu: shrank the ram size and address bus to 16kJosh Blum2010-12-061-5/+5
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* | | zpu: added a zpu + wishbone opencore and integrated into top levelJosh Blum2010-12-061-10/+18
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* | packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-1/+1
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* | packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-1/+1
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* | packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-231-16/+27
| | | | | | | | udp_wrapper in top level with some fifo conversion stuff
* | packet_router: implemented crossbar and valve module, moved sreg into router ↵Josh Blum2010-11-231-16/+7
| | | | | | | | module
* | packet_router: transplanted the async error interface, its now sent into the ↵Josh Blum2010-11-231-10/+5
| | | | | | | | packet router to be muxed to com out
* | packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-1/+3
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* | packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-2/+4
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* | packet_router: removed unused status words from readback muxJosh Blum2010-11-231-3/+3
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* | packet_router: fixed swapped connection typo, dsp tx routing worksJosh Blum2010-11-231-2/+3
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* | packet_router: added all input/output signals to module, created the comm ↵Josh Blum2010-11-231-0/+3
| | | | | | | | muxes (in and out)
* | packet_router: created inspector and added dsp output (however inspection ↵Josh Blum2010-11-231-0/+1
| | | | | | | | logic does not enable it yet)
* | packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-231-19/+14
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* shouldn't be executableMatt Ettus2010-11-201-0/+0
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* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-111-4/+1
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* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-111-11/+12
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-111-3/+9
| | | | style fifo in rx.
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
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* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
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* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-111-1/+2
| | | | without flow control
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-32/+32
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* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
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* Modified phase shift of DCM1 to -64 which is intended to give more timing ↵Ian Buckley2010-11-111-1/+1
| | | | | | | margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
* Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵Ian Buckley2010-11-111-12/+12
| | | | | | | | SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-11-114-5/+100
| | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
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