uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	settings bus to dsp_clk now uses clock crossing fifo	Matt Ettus	2010-05-16	1	-0/+3
*	Update config to all eight clock buffers to be used.	Johnathan Corgan	2010-03-29	1	-1/+1
*	Added timing constraint for Wishbone clock/dsp_clock skew	Johnathan Corgan	2010-03-29	1	-0/+2
*	Cut debug bus connection to etherenet MAC to make closing timing easier	Ian Buckley	2010-02-24	1	-2/+7
*	Manually assign clk_fpga to BUFG to improve timing	Johnathan Corgan	2010-02-23	1	-1/+5
*	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	4	-0/+1068