| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge branch 'cordic_policy' into next | Josh Blum | 2011-01-04 | 1 | -20/+15 |
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| | * | hook up sampled pps in u2plus, remove unused priority encoder, minor cleanups | Matt Ettus | 2010-12-30 | 1 | -12/+10 |
| | * | processor can read back vita_time at last pps | Matt Ettus | 2010-12-30 | 1 | -10/+4 |
| * | | Merge branch 'udp_ports' into next | Josh Blum | 2010-12-22 | 1 | -1/+2 |
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| | * | | generate port number headers in the dsp error units | Matt Ettus | 2010-12-15 | 1 | -1/+2 |
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| * | | usrp-n210: almost working w/ packet router + zpu | Josh Blum | 2010-12-17 | 1 | -13/+3 |
| * | | zpu: working, modified top level sizes, disable interrupt | Josh Blum | 2010-12-14 | 2 | -8/+5 |
| * | | Merge branch 'packet_router' into zpu | Josh Blum | 2010-12-12 | 5 | -121/+28 |
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| | * | | Merge branch 'ise12' into packet_router | Josh Blum | 2010-12-10 | 4 | -23/+26 |
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| | | * | time sync on usrp2 as well, added debug pins to time sync. | Matt Ettus | 2010-12-10 | 1 | -1/+5 |
| | | * | Only do udp now, renamed old ports to exp_time_* | Matt Ettus | 2010-12-09 | 1 | -0/+0 |
| | | * | udp is now the default | Matt Ettus | 2010-12-09 | 2 | -2/+2 |
| | | * | remove old raw ethernet version | Matt Ettus | 2010-12-09 | 2 | -882/+0 |
| | | * | renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signal | Matt Ettus | 2010-12-09 | 3 | -18/+18 |
| | * | | packet_router: renamed top level files in an attempt to merge cleanly | Josh Blum | 2010-12-10 | 4 | -1091/+209 |
| * | | | zpu: moved top level file in hopes for easy merge | Josh Blum | 2010-12-12 | 2 | -1014/+229 |
| * | | | zpu: moved stack pointer and made connection for status | Josh Blum | 2010-12-06 | 1 | -1/+2 |
| * | | | zpu: shrank the ram size and address bus to 16k | Josh Blum | 2010-12-06 | 1 | -5/+5 |
| * | | | zpu: added a zpu + wishbone opencore and integrated into top level | Josh Blum | 2010-12-06 | 1 | -10/+18 |
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| * | | packet_router: added status readback for mode, incremented compat number | Josh Blum | 2010-11-24 | 1 | -1/+1 |
| * | | packet_router: program the dsp udp port and ip addr through setting registers | Josh Blum | 2010-11-23 | 1 | -1/+1 |
| * | | packet_router: moved udp tx proto machine into packet router, replaced udp_wr... | Josh Blum | 2010-11-23 | 1 | -16/+27 |
| * | | packet_router: implemented crossbar and valve module, moved sreg into router ... | Josh Blum | 2010-11-23 | 1 | -16/+7 |
| * | | packet_router: transplanted the async error interface, its now sent into the ... | Josh Blum | 2010-11-23 | 1 | -10/+5 |
| * | | packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debug | Josh Blum | 2010-11-23 | 1 | -1/+3 |
| * | | packet_router: registered control flags, added clear to all state machines | Josh Blum | 2010-11-23 | 1 | -2/+4 |
| * | | packet_router: removed unused status words from readback mux | Josh Blum | 2010-11-23 | 1 | -3/+3 |
| * | | packet_router: fixed swapped connection typo, dsp tx routing works | Josh Blum | 2010-11-23 | 1 | -2/+3 |
| * | | packet_router: added all input/output signals to module, created the comm mux... | Josh Blum | 2010-11-23 | 1 | -0/+3 |
| * | | packet_router: created inspector and added dsp output (however inspection log... | Josh Blum | 2010-11-23 | 1 | -0/+1 |
| * | | packet_router: created nearly empty router with eth in attached to mapped memory | Josh Blum | 2010-11-23 | 1 | -19/+14 |
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| * | shouldn't be executable | Matt Ettus | 2010-11-20 | 1 | -0/+0 |
| * | Add flow control and other small vrt fixes to u2p, minor cleanups | Matt Ettus | 2010-11-11 | 1 | -4/+1 |
| * | clear out the vita tx chain and the tx fifo. need to check the fifo | Matt Ettus | 2010-11-11 | 1 | -11/+12 |
| * | added ability to truly clear out the entire rx chain. also removed old style... | Matt Ettus | 2010-11-11 | 1 | -3/+9 |
| * | proper triggering for interrupts generated on the dsp_clk | Matt Ettus | 2010-11-11 | 1 | -1/+8 |
| * | increase compatibility number for flow control | Matt Ettus | 2010-11-11 | 1 | -1/+1 |
| * | separated flow control and error reporting on tx path. should work with and ... | Matt Ettus | 2010-11-11 | 1 | -1/+2 |
| * | revert unneeded changes and incorrect comments | Matt Ettus | 2010-11-11 | 1 | -32/+32 |
| * | reconnect GPIOs, remove debug pins, meets timing now | Matt Ettus | 2010-11-11 | 1 | -5/+3 |
| * | Modified phase shift of DCM1 to -64 which is intended to give more timing mar... | Ian Buckley | 2010-11-11 | 1 | -1/+1 |
| * | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S... | Ian Buckley | 2010-11-11 | 1 | -12/+12 |
| * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i... | Ian Buckley | 2010-11-11 | 4 | -5/+100 |
| * | hangedddddddextrnal fifo size to use full NoBL SRAM | ianb | 2010-11-11 | 1 | -1/+1 |
| * | Corrected extfifo code so that all registers that are on SRAM signals are pac... | ianb | 2010-11-11 | 2 | -37/+42 |
| * | Added a bunch of debug signals. | Ian Buckley | 2010-11-11 | 1 | -4/+5 |
| * | Regenerated FIFO with lower trigger level for almost full flag to reflect log... | Ian Buckley | 2010-11-11 | 1 | -1/+2 |
| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-11-11 | 4 | -142/+200 |
| * | remove old commented out code | Matt Ettus | 2010-11-09 | 1 | -180/+0 |
| * | fix timing problem on DAC output bus | Matt Ettus | 2010-11-09 | 1 | -2/+2 |
