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* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-144-412/+1734
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| * produces good bin filesMatt Ettus2010-06-112-12/+20
| * first attempt at cleaning up the build systemMatt Ettus2010-06-103-414/+65
| * get rid of debug stuff to help timingMatt Ettus2010-06-081-7/+16
| * move u2_core into u2_rev3 directory to simplify directory structure and save ...Matt Ettus2010-06-084-2/+1657
* | Merge branch 'master' into u1eMatt Ettus2010-06-082-2/+2
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| * report ise version in buildMatt Ettus2010-06-071-1/+1
| * proper name for directoryMatt Ettus2010-06-071-1/+1
| * name build directory with ISE version nameMatt Ettus2010-06-071-1/+1
* | Merge branch 'master_nocache' into master_nocache_post_mergeMatt Ettus2010-05-282-0/+2
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| * removes the icache and pipelines the readsMatt Ettus2010-05-201-0/+1
* | from UDP branch, changed names because I want these separate from the non-udp...Matt Ettus2010-05-271-0/+267
* | new files from udp branch added to main MakefileMatt Ettus2010-05-271-1/+19
* | Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-271-1/+1
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| * ignoresMatt Ettus2010-05-181-1/+1
| * move dsp settings regs to reclocked setting bus. Works, gets us to within 18...Matt Ettus2010-05-121-0/+3
| * Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-263-4/+15
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udpMatt Ettus2010-01-251-2/+1
| * | moved into subdirJosh Blum2010-01-224-0/+1085
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* / settings bus to dsp_clk now uses clock crossing fifoMatt Ettus2010-05-161-0/+3
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* Update config to all eight clock buffers to be used.Johnathan Corgan2010-03-291-1/+1
* Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
* Cut debug bus connection to etherenet MAC to make closing timing easierIan Buckley2010-02-241-2/+7
* Manually assign clk_fpga to BUFG to improve timingJohnathan Corgan2010-02-231-1/+5
* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-224-0/+1068
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