uhd - Ettus' UHD Repository

	Commit message (Expand)	Author	Age	Files	Lines
*	clean up DAC inversion and swapping to match schematics	Matt Ettus	2010-08-25	1	-3/+6
*	Clean up iq swapping on RX. It is now swapped in the top level.	Matt Ettus	2010-08-25	2	-5/+5
*	added compat number to usrp2 readback mux	Josh Blum	2010-08-09	1	-2/+5
*	connect the demux	Matt Ettus	2010-07-28	1	-1/+1
*	fix a typo	Matt Ettus	2010-07-28	1	-1/+1
*	tx error packets now muxed into the ethernet stream back to the host	Matt Ettus	2010-07-28	1	-27/+22
*	move declaration ahead of use	Matt Ettus	2010-07-19	1	-5/+5
*	put run_tx and run_rx on the displayed LEDs	Matt Ettus	2010-07-19	1	-3/+4
*	barely fails timing on gigE/10 and gigE/12, larger fail on udp/10, but all	Matt Ettus	2010-06-14	2	-52/+51
*	produces good bin files	Matt Ettus	2010-06-11	2	-12/+20
*	first attempt at cleaning up the build system	Matt Ettus	2010-06-10	3	-414/+65
*	get rid of debug stuff to help timing	Matt Ettus	2010-06-08	1	-7/+16
*	move u2_core into u2_rev3 directory to simplify directory structure and save ...	Matt Ettus	2010-06-08	4	-2/+1657
*	report ise version in build	Matt Ettus	2010-06-07	1	-1/+1
*	proper name for directory	Matt Ettus	2010-06-07	1	-1/+1
*	name build directory with ISE version name	Matt Ettus	2010-06-07	1	-1/+1
*	from UDP branch, changed names because I want these separate from the non-udp...	Matt Ettus	2010-05-27	1	-0/+267
*	new files from udp branch added to main Makefile	Matt Ettus	2010-05-27	1	-1/+19
*	Merge branch 'udp' into master_merge_take2	Matt Ettus	2010-05-27	1	-1/+1
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\| *	ignores	Matt Ettus	2010-05-18	1	-1/+1
\| *	move dsp settings regs to reclocked setting bus. Works, gets us to within 18...	Matt Ettus	2010-05-12	1	-0/+3
\| *	Merge branch 'corgan_fixes' into udp_corgan	Matt Ettus	2010-04-26	3	-4/+15
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\| * \|	Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp	Matt Ettus	2010-01-25	1	-2/+1
\| * \|	moved into subdir	Josh Blum	2010-01-22	4	-0/+1085
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* /	settings bus to dsp_clk now uses clock crossing fifo	Matt Ettus	2010-05-16	1	-0/+3
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*	Update config to all eight clock buffers to be used.	Johnathan Corgan	2010-03-29	1	-1/+1
*	Added timing constraint for Wishbone clock/dsp_clock skew	Johnathan Corgan	2010-03-29	1	-0/+2
*	Cut debug bus connection to etherenet MAC to make closing timing easier	Ian Buckley	2010-02-24	1	-2/+7
*	Manually assign clk_fpga to BUFG to improve timing	Johnathan Corgan	2010-02-23	1	-1/+5
*	Moved usrp2 fpga files into usrp2 subdir.	Josh Blum	2010-01-22	4	-0/+1068