| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| | * | Merge branch 'corgan_fixes' into udp_corgan | Matt Ettus | 2010-04-26 | 3 | -4/+15 | |
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| | * | | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 1 | -2/+1 | |
| | * | | moved into subdir | Josh Blum | 2010-01-22 | 4 | -0/+1085 | |
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| * / | settings bus to dsp_clk now uses clock crossing fifo | Matt Ettus | 2010-05-16 | 1 | -0/+3 | |
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| * | Update config to all eight clock buffers to be used. | Johnathan Corgan | 2010-03-29 | 1 | -1/+1 | |
| * | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 | |
| * | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 | |
| * | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 | |
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 4 | -0/+1068 | |
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