aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/top/u2_rev3
Commit message (Collapse)AuthorAgeFilesLines
* usrp-n210: almost working w/ packet router + zpuJosh Blum2010-12-171-13/+3
| | | | | | | added stack start signal to zpu removed wb perifs in n210 out of 0-16k added reset controller for main app rewire cpu addr line after booted use 0-16k
* zpu: working, modified top level sizes, disable interruptJosh Blum2010-12-142-8/+5
|
* Merge branch 'packet_router' into zpuJosh Blum2010-12-125-121/+28
|\ | | | | | | | | Conflicts: usrp2/top/u2_rev3/u2_core.v
| * Merge branch 'ise12' into packet_routerJosh Blum2010-12-104-23/+26
| |\ | | | | | | | | | | | | | | | Conflicts: usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/u2_core.v
| | * time sync on usrp2 as well, added debug pins to time sync.Matt Ettus2010-12-101-1/+5
| | |
| | * Only do udp now, renamed old ports to exp_time_*Matt Ettus2010-12-091-0/+0
| | |
| | * udp is now the defaultMatt Ettus2010-12-092-2/+2
| | |
| | * remove old raw ethernet versionMatt Ettus2010-12-092-882/+0
| | |
| | * renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-093-18/+18
| | |
| * | packet_router: renamed top level files in an attempt to merge cleanlyJosh Blum2010-12-104-1091/+209
| | |
* | | zpu: moved top level file in hopes for easy mergeJosh Blum2010-12-122-1014/+229
| | |
* | | zpu: moved stack pointer and made connection for statusJosh Blum2010-12-061-1/+2
| | |
* | | zpu: shrank the ram size and address bus to 16kJosh Blum2010-12-061-5/+5
| | |
* | | zpu: added a zpu + wishbone opencore and integrated into top levelJosh Blum2010-12-061-10/+18
|/ /
* | packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-1/+1
| |
* | packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-1/+1
| |
* | packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-231-16/+27
| | | | | | | | udp_wrapper in top level with some fifo conversion stuff
* | packet_router: implemented crossbar and valve module, moved sreg into router ↵Josh Blum2010-11-231-16/+7
| | | | | | | | module
* | packet_router: transplanted the async error interface, its now sent into the ↵Josh Blum2010-11-231-10/+5
| | | | | | | | packet router to be muxed to com out
* | packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-1/+3
| |
* | packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-2/+4
| |
* | packet_router: removed unused status words from readback muxJosh Blum2010-11-231-3/+3
| |
* | packet_router: fixed swapped connection typo, dsp tx routing worksJosh Blum2010-11-231-2/+3
| |
* | packet_router: added all input/output signals to module, created the comm ↵Josh Blum2010-11-231-0/+3
| | | | | | | | muxes (in and out)
* | packet_router: created inspector and added dsp output (however inspection ↵Josh Blum2010-11-231-0/+1
| | | | | | | | logic does not enable it yet)
* | packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-231-19/+14
|/
* shouldn't be executableMatt Ettus2010-11-201-0/+0
|
* Add flow control and other small vrt fixes to u2p, minor cleanupsMatt Ettus2010-11-111-4/+1
|
* clear out the vita tx chain and the tx fifo. need to check the fifoMatt Ettus2010-11-111-11/+12
| | | | reset to make sure it is in the correct clock domain.
* added ability to truly clear out the entire rx chain. also removed old ↵Matt Ettus2010-11-111-3/+9
| | | | style fifo in rx.
* proper triggering for interrupts generated on the dsp_clkMatt Ettus2010-11-111-1/+8
|
* increase compatibility number for flow controlMatt Ettus2010-11-111-1/+1
|
* separated flow control and error reporting on tx path. should work with and ↵Matt Ettus2010-11-111-1/+2
| | | | without flow control
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-32/+32
|
* reconnect GPIOs, remove debug pins, meets timing nowMatt Ettus2010-11-111-5/+3
|
* Modified phase shift of DCM1 to -64 which is intended to give more timing ↵Ian Buckley2010-11-111-1/+1
| | | | | | | margin on reads from the SRAM at the expense of Writes to the SRAM. Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer. Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
* Enabled phase offset adjustment on DCM_INST1 which drives the external Fast ↵Ian Buckley2010-11-111-12/+12
| | | | | | | | SRAM clock. Set phase shift to -12 after experimentation using logic analyzer to see results. This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM under lab conditions.
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-11-114-5/+100
| | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
* hangedddddddextrnal fifo size to use full NoBL SRAMianb2010-11-111-1/+1
|
* Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-11-112-37/+42
| | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
* Added a bunch of debug signals.Ian Buckley2010-11-111-4/+5
|
* Regenerated FIFO with lower trigger level for almost full flag to reflect ↵Ian Buckley2010-11-111-1/+2
| | | | | | | | | | | | | logic removed from nobl_fifo. Improved ext_fifo_tb further, try to simulate more combinations of decomation rates and packet arrival patterns. Strip out the logic in nobl_fifo that made it look like a Xilinx fall-through FIFO...it is now very simple logic but a propriatory interface that exposes the high inetrnal latency of reads. Allow the USED size of the external FIFO to be parameterized from the core level. Currently set at only 256 Corrected a bug in vita_tx_deframer.v that can write to a FIFO when its full causing illegal state. Made further edits that are currently commented becuase simulation indicates they cause problems, however suspect a further bug is in this code.
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-11-114-142/+200
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* remove old commented out codeMatt Ettus2010-11-091-180/+0
|
* fix timing problem on DAC output busMatt Ettus2010-11-091-2/+2
|
* clean up DAC inversion and swapping to match schematicsMatt Ettus2010-08-251-3/+6
|
* Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-252-5/+5
| | | | widened muxes to 4 bits to match tx side and handle more ADCs in future
* added compat number to usrp2 readback muxJosh Blum2010-08-091-2/+5
|
* connect the demuxMatt Ettus2010-07-281-1/+1
|
* fix a typoMatt Ettus2010-07-281-1/+1
|
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-05 21:25:27 +0000