| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'master' into u1e | Matt Ettus | 2010-05-12 | 3 | -4/+15 |
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| | * | Update config to all eight clock buffers to be used. | Johnathan Corgan | 2010-03-29 | 1 | -1/+1 |
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| | * | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 |
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| | * | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 |
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| | * | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Router Phase 1: 96908 unrouted; REAL time: 25 secs Phase 2: 85651 unrouted; REAL time: 35 secs Phase 3: 27099 unrouted; REAL time: 49 secs Phase 4: 27099 unrouted; (97405) REAL time: 49 secs Phase 5: 27259 unrouted; (5348) REAL time: 54 secs Phase 6: 27277 unrouted; (0) REAL time: 54 secs Phase 7: 0 unrouted; (0) REAL time: 1 mins 46 secs Phase 8: 0 unrouted; (0) REAL time: 1 mins 56 secs Phase 9: 0 unrouted; (0) REAL time: 2 mins 29 secs | ||||
| | * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 4 | -0/+1068 |
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| * | Merge commit '8d19387a8642caf74179bdcb7eddf1936f473e53' into udp | Matt Ettus | 2010-01-25 | 1 | -2/+1 |
| | | | | | | | | | Merge latest VRT changes into UDP branch. Merged from 1 behind the head of VRT because the head moved things around and confused git Conflicts: usrp2/timing/time_64bit.v usrp2/top/u2_core/u2_core.v | ||||
| * | moved into subdir | Josh Blum | 2010-01-22 | 4 | -0/+1085 |
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