| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-07-31 | 1 | -94/+127 |
| * | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 |
| * | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 |
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 1 | -0/+432 |
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