| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Modified phase shift of DCM1 to -64 which is intended to give more timing mar... | Ian Buckley | 2010-11-11 | 1 | -1/+1 |
| * | Enabled phase offset adjustment on DCM_INST1 which drives the external Fast S... | Ian Buckley | 2010-11-11 | 1 | -12/+12 |
| * | Added to DCM's and some BUFG's to align the internal 125MHz clock edge with i... | Ian Buckley | 2010-11-11 | 1 | -2/+97 |
| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with cu... | Ian Buckley | 2010-11-11 | 1 | -94/+127 |
| * | fix timing problem on DAC output bus | Matt Ettus | 2010-11-09 | 1 | -2/+2 |
| * | clean up DAC inversion and swapping to match schematics | Matt Ettus | 2010-08-25 | 1 | -3/+6 |
| * | Clean up iq swapping on RX. It is now swapped in the top level. | Matt Ettus | 2010-08-25 | 1 | -4/+4 |
| * | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 |
| * | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 |
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 1 | -0/+432 |
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