aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/top/u2_rev3/u2_rev3.ucf
Commit message (Collapse)AuthorAgeFilesLines
* renamed exp_pps_* to be exp_time_*, which is the mimo synchronization signalMatt Ettus2010-12-091-4/+4
|
* revert unneeded changes and incorrect commentsMatt Ettus2010-11-111-32/+32
|
* Added to DCM's and some BUFG's to align the internal 125MHz clock edge with ↵Ian Buckley2010-11-111-0/+1
| | | | | | | its presentation externally at the NoBL SRAM. Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA. This hasn't been verified as working on a USRP2 yet.
* Corrected extfifo code so that all registers that are on SRAM signals are ↵ianb2010-11-111-32/+32
| | | | | | | | packed into IOBs Explcit drives and skews added to GPIO pins Corrected minor error in FIFO logic that showed data avail internally incorrectly
* External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-11-111-43/+43
| | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* Added timing constraint for Wishbone clock/dsp_clock skewJohnathan Corgan2010-03-291-0/+2
|
* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-221-0/+333
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-11 15:41:09 +0000