uhd - Ettus' UHD Repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵	Matt Ettus	2010-03-26	3	-8/+26
\| \| \| \|	be read/controlled from SW
*	connected spi pins, but the spi core still needs to be redone for 16 bit ↵	Matt Ettus	2010-03-25	3	-40/+60
\| \| \| \| \| \|	interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
*	debug pins	Matt Ettus	2010-02-25	1	-2/+3
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*	invert the pushbuttons since they are active low	Matt Ettus	2010-02-25	1	-2/+2
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*	gpmc debug pins	Matt Ettus	2010-02-25	1	-3/+6
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*	point to the new files	Matt Ettus	2010-02-25	1	-0/+2
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*	loopback and test	Matt Ettus	2010-02-25	1	-2/+32
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*	First cut at passing data buffers around on GPMC bus	Matt Ettus	2010-02-25	3	-10/+24
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*	first cut at making a bidirectional 2 port ram for the gpmc data interface	Matt Ettus	2010-02-23	1	-0/+1
\| \| \| \|	ISE chokes on the unequal size ram
*	use our fancy new debug ports	Matt Ettus	2010-02-23	1	-0/+3
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*	settings bus with 16 bit wishbone interface, put on the main wishbone in u1e	Matt Ettus	2010-02-22	2	-3/+14
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*	GPIOs now on the wishbone interface	Matt Ettus	2010-02-22	4	-37/+54
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*	added gpio control to the wishbone	Matt Ettus	2010-02-18	2	-11/+14
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*	Added I2C, UART, debug pins, misc wishbone stuff	Matt Ettus	2010-02-18	3	-48/+187
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*	Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵	Matt Ettus	2010-02-18	2	-4/+7
\| \| \| \|	global set and reset module.
*	wishbone bridge now with minimal functionality. Need to check	Matt Ettus	2010-02-16	6	-9/+49
\| \| \| \|	timing and handle wait states.
*	first cut at gpmc <-> wb bridge, split u1e into core, top, and tb	Matt Ettus	2010-02-16	5	-34/+93
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*	copied over from safe_u1e	Matt Ettus	2010-02-16	4	-0/+553