| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | better debug pins | Matt Ettus | 2010-05-17 | 1 | -6/+4 |
| * | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet... | Matt Ettus | 2010-05-12 | 2 | -22/+43 |
| * | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_... | Matt Ettus | 2010-05-10 | 1 | -1/+1 |
| * | proper signal level for 24 bit data | Matt Ettus | 2010-05-10 | 1 | -2/+7 |
| * | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 3 | -18/+63 |
| * | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
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| | * | add timing constraints. Just have main clock signal at 64 MHz for now. | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
| * | | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 |
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| * | separate timed tx and rx instead of loopback | Matt Ettus | 2010-04-28 | 1 | -3/+51 |
| * | send bus error to debug pins | Matt Ettus | 2010-04-26 | 1 | -2/+4 |
| * | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 3 | -16/+21 |
| * | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 |
| * | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 |
| * | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 1 | -6/+14 |
| * | async seems to work with packet lengths now. Still need to do wishbone regs ... | Matt Ettus | 2010-04-15 | 1 | -3/+3 |
| * | async gpmc progress | Matt Ettus | 2010-04-15 | 2 | -18/+20 |
| * | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 1 | -1/+1 |
| * | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 1 | -0/+2 |
| * | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 1 | -0/+1 |
| * | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 1 | -1/+1 |
| * | added in a loopback fifo | Matt Ettus | 2010-04-14 | 1 | -4/+11 |
| * | minor changes to get it to synthesize | Matt Ettus | 2010-04-13 | 1 | -0/+3 |
| * | replaced ram interface with a fifo interface. still need to do rx side | Matt Ettus | 2010-04-12 | 1 | -39/+7 |
| * | added 16-bit wide atr controller | Matt Ettus | 2010-04-01 | 2 | -33/+44 |
| * | connect up the 16 bit spi core | Matt Ettus | 2010-03-26 | 2 | -5/+4 |
| * | connect 2 clock gen controls and 3 status pins to the wishbone so they can be... | Matt Ettus | 2010-03-26 | 3 | -8/+26 |
| * | connected spi pins, but the spi core still needs to be redone for 16 bit inte... | Matt Ettus | 2010-03-25 | 3 | -40/+60 |
| * | debug pins | Matt Ettus | 2010-02-25 | 1 | -2/+3 |
| * | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
| * | gpmc debug pins | Matt Ettus | 2010-02-25 | 1 | -3/+6 |
| * | point to the new files | Matt Ettus | 2010-02-25 | 1 | -0/+2 |
| * | loopback and test | Matt Ettus | 2010-02-25 | 1 | -2/+32 |
| * | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 3 | -10/+24 |
| * | first cut at making a bidirectional 2 port ram for the gpmc data interface | Matt Ettus | 2010-02-23 | 1 | -0/+1 |
| * | use our fancy new debug ports | Matt Ettus | 2010-02-23 | 1 | -0/+3 |
| * | settings bus with 16 bit wishbone interface, put on the main wishbone in u1e | Matt Ettus | 2010-02-22 | 2 | -3/+14 |
| * | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 4 | -37/+54 |
| * | added gpio control to the wishbone | Matt Ettus | 2010-02-18 | 2 | -11/+14 |
| * | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 3 | -48/+187 |
| * | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx gl... | Matt Ettus | 2010-02-18 | 2 | -4/+7 |
| * | wishbone bridge now with minimal functionality. Need to check | Matt Ettus | 2010-02-16 | 6 | -9/+49 |
| * | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 5 | -34/+93 |
| * | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 4 | -0/+553 |
