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* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
* added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
* connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
* connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
* debug pinsMatt Ettus2010-02-251-2/+3
* invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
* gpmc debug pinsMatt Ettus2010-02-251-3/+6
* point to the new filesMatt Ettus2010-02-251-0/+2
* loopback and testMatt Ettus2010-02-251-2/+32
* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-253-10/+24
* first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+1
* use our fancy new debug portsMatt Ettus2010-02-231-0/+3
* settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-222-3/+14
* GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
* added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
* Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
* Fixed paths to help icarus find opencores and xilinx models. Added Xilinx gl...Matt Ettus2010-02-182-4/+7
* wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-166-9/+49
* first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-165-34/+93
* copied over from safe_u1eMatt Ettus2010-02-164-0/+553