| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | u1e: switch to vita_rx_chain module just like other toplevels | Matt Ettus | 2011-05-09 | 2 | -20/+11 |
| * | u1e: use icarus verilog for lint | Matt Ettus | 2011-03-16 | 1 | -0/+2 |
| * | clean up a bunch of warnings and incorrect bus widths | Matt Ettus | 2011-03-16 | 1 | -5/+6 |
| * | u1e: removed old directory from make | Matt Ettus | 2011-03-15 | 1 | -1/+0 |
| * | u1e: keep up with fixes made for u2/u2p, make it compile again | Matt Ettus | 2011-03-15 | 1 | -1/+0 |
| * | timed tester : Bring out src/dst flags for rx chain for testing. | Philip Balister | 2011-02-25 | 1 | -0/+4 |
| * | u1e: hook up tester controls | Matt Ettus | 2011-02-17 | 1 | -4/+6 |
| * | hook up under/overruns for debug purposes | Matt Ettus | 2011-02-16 | 1 | -3/+7 |
| * | e100: integrate loopback and timed testing into main image | Matt Ettus | 2011-02-16 | 1 | -74/+1 |
| * | separate clear for tx and rx, and add a global reset from the host | Matt Ettus | 2011-02-02 | 1 | -10/+19 |
| * | usrp-e100: added missing newfifo files to list, added missing signals for timed | Josh Blum | 2011-01-26 | 1 | -1/+2 |
| * | usrp-e100: added 32bit test read/write register, fixes to get building | Josh Blum | 2011-01-25 | 1 | -7/+17 |
| * | reorganized u1e register space to make room for 64 settingregs | Matt Ettus | 2011-01-25 | 1 | -12/+15 |
| * | usrp-e100: added readback mux 32 as slave 7 for time readback | Josh Blum | 2011-01-14 | 1 | -4/+16 |
| * | invert led signals because they are active low | Matt Ettus | 2010-11-09 | 1 | -1/+1 |
| * | duh | Matt Ettus | 2010-11-04 | 1 | -1/+1 |
| * | watch the ethernet chip select on our debug bus | Matt Ettus | 2010-09-23 | 3 | -6/+8 |
| * | fix timing issue on DAC outputs with rev 2. This puts the whole system on a ... | Matt Ettus | 2010-09-21 | 2 | -50/+25 |
| * | updated pins to match rev2, removed dip switch, etc. seems to compile ok. | Matt Ettus | 2010-09-09 | 3 | -137/+130 |
| * | add register to tell host about compatibility level and which image we are using | Matt Ettus | 2010-08-30 | 1 | -5/+14 |
| * | move declaration to make loopback compile | Matt Ettus | 2010-08-27 | 1 | -1/+2 |
| * | no need for protocol headers since we're not doing ethernet | Matt Ettus | 2010-08-24 | 1 | -1/+1 |
| * | match the signal names in this design | Matt Ettus | 2010-08-23 | 1 | -3/+3 |
| * | debug pins cleanup | Matt Ettus | 2010-08-23 | 1 | -3/+3 |
| * | properly integrate the new tx chain | Matt Ettus | 2010-08-19 | 1 | -31/+27 |
| * | attach run_tx and run_rx to leds | Matt Ettus | 2010-08-17 | 1 | -1/+1 |
| * | connect atr | Matt Ettus | 2010-08-17 | 1 | -1/+1 |
| * | delay the q channel to make the channels line up on the AD9862 | Matt Ettus | 2010-08-17 | 1 | -1/+6 |
| * | this is necessary for some reason | Matt Ettus | 2010-08-13 | 1 | -1/+2 |
| * | connect the setting reg to the real clock and reset | Matt Ettus | 2010-08-11 | 1 | -1/+1 |
| * | enlarge loopback fifo | Matt Ettus | 2010-08-10 | 1 | -4/+1 |
| * | make loopback compile | Matt Ettus | 2010-07-14 | 1 | -0/+3 |
| * | added ability to clear out fifos of tx and rx. | Matt Ettus | 2010-06-17 | 1 | -12/+21 |
| * | Merge branch 'master' into u1e_newbuild | Matt Ettus | 2010-06-14 | 1 | -206/+39 |
| * | debug pins | Matt Ettus | 2010-06-10 | 1 | -3/+6 |
| * | much bigger fifos | Matt Ettus | 2010-06-10 | 1 | -2/+2 |
| * | proper overrun, underrun connections, debug pins. | Matt Ettus | 2010-06-10 | 1 | -4/+8 |
| * | debug pins | Matt Ettus | 2010-06-08 | 1 | -1/+2 |
| * | remove double declaration | Matt Ettus | 2010-06-06 | 1 | -1/+1 |
| * | use fifo19 not fifo18 in makefile | Matt Ettus | 2010-06-06 | 1 | -1/+1 |
| * | use same version as usrp2-udp, so regs are same place in memory map | Matt Ettus | 2010-06-01 | 2 | -2/+2 |
| * | connect the rx run lines so it doesn't get optimized out | Matt Ettus | 2010-06-01 | 1 | -1/+4 |
| * | use DDR regs instead of a 2nd clock | Matt Ettus | 2010-06-01 | 1 | -8/+46 |
| * | assign addresses for the settings regs | Matt Ettus | 2010-06-01 | 1 | -5/+6 |
| * | vita49 tx and rx added in, all sample rates now at main system clock rate. | Matt Ettus | 2010-06-01 | 4 | -107/+220 |
| * | send bigger packets to reduce cpu load | Matt Ettus | 2010-05-20 | 1 | -2/+2 |
| * | put over/underrun on debug bus, remove high order address bits | Matt Ettus | 2010-05-20 | 1 | -1/+2 |
| * | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-20 | 1 | -4/+2 |
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| | * | better debug pins | Matt Ettus | 2010-05-17 | 1 | -6/+4 |
| * | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rate | Matt Ettus | 2010-05-20 | 2 | -34/+24 |
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