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Commit message (Collapse)AuthorAgeFilesLines
* debug pinsMatt Ettus2010-06-081-1/+2
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* remove double declarationMatt Ettus2010-06-061-1/+1
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* use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
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* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
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* connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
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* use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
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* assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
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* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
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* send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
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* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
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* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\ | | | | | | | | Conflicts: usrp2/top/u1e/u1e_core.v
| * better debug pinsMatt Ettus2010-05-171-6/+4
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* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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* moved fifos into gpmc_async, reorganized top level a bit, added in crc ↵Matt Ettus2010-05-122-22/+43
| | | | packet gen and test
* switched passthru of cgen_sen_b to gpio127, made a note of it. No more ↵Matt Ettus2010-05-101-1/+1
| | | | safe_u1e necessary.
* proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
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* added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
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* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
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* | changed commentMatt Ettus2010-05-041-1/+1
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* separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
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* send bus error to debug pinsMatt Ettus2010-04-261-2/+4
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* Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
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* find time_64bitMatt Ettus2010-04-201-0/+1
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* added pps and time capabilityMatt Ettus2010-04-153-5/+21
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* access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
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* async seems to work with packet lengths now. Still need to do wishbone regs ↵Matt Ettus2010-04-151-3/+3
| | | | for gpmc
* async gpmc progressMatt Ettus2010-04-152-18/+20
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* synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
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* handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
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* more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
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* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
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* added in a loopback fifoMatt Ettus2010-04-141-4/+11
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* minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
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* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
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* added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
| | | | | settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
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* connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵Matt Ettus2010-03-263-8/+26
| | | | be read/controlled from SW
* connected spi pins, but the spi core still needs to be redone for 16 bit ↵Matt Ettus2010-03-253-40/+60
| | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs
* debug pinsMatt Ettus2010-02-251-2/+3
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* invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
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* gpmc debug pinsMatt Ettus2010-02-251-3/+6
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* point to the new filesMatt Ettus2010-02-251-0/+2
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* loopback and testMatt Ettus2010-02-251-2/+32
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* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-253-10/+24
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* first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+1
| | | | ISE chokes on the unequal size ram
* use our fancy new debug portsMatt Ettus2010-02-231-0/+3
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* settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-222-3/+14
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* GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
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* added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
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