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* connect atrMatt Ettus2010-08-171-1/+1
* delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
* this is necessary for some reasonMatt Ettus2010-08-131-1/+2
* connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
* enlarge loopback fifoMatt Ettus2010-08-101-4/+1
* make loopback compileMatt Ettus2010-07-141-0/+3
* added ability to clear out fifos of tx and rx.Matt Ettus2010-06-171-12/+21
* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-206/+39
* debug pinsMatt Ettus2010-06-101-3/+6
* much bigger fifosMatt Ettus2010-06-101-2/+2
* proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
* debug pinsMatt Ettus2010-06-081-1/+2
* remove double declarationMatt Ettus2010-06-061-1/+1
* use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
* connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
* use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
* assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
* send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
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| * better debug pinsMatt Ettus2010-05-171-6/+4
* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
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* moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
* switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-101-1/+1
* proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
* added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
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| * add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
* | changed commentMatt Ettus2010-05-041-1/+1
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* separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
* send bus error to debug pinsMatt Ettus2010-04-261-2/+4
* Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-243-16/+21
* find time_64bitMatt Ettus2010-04-201-0/+1
* added pps and time capabilityMatt Ettus2010-04-153-5/+21
* access frame length regs from wishboneMatt Ettus2010-04-151-6/+14
* async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-151-3/+3
* async gpmc progressMatt Ettus2010-04-152-18/+20
* synchronous and asynchronous gpmc modelsMatt Ettus2010-04-151-1/+1
* handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
* more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
* added in a loopback fifoMatt Ettus2010-04-141-4/+11
* minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-121-39/+7
* added 16-bit wide atr controllerMatt Ettus2010-04-012-33/+44
* connect up the 16 bit spi coreMatt Ettus2010-03-262-5/+4
* connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-263-8/+26
* connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-253-40/+60
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