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path: root/usrp2/top/u1e/u1e.v
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* added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-041-0/+4
* Pass previously unused GPIOs to debug pins to help debug interruptsMatt Ettus2010-04-241-0/+7
* added pps and time capabilityMatt Ettus2010-04-151-2/+4
* connect 2 clock gen controls and 3 status pins to the wishbone so they can be...Matt Ettus2010-03-261-0/+4
* connected spi pins, but the spi core still needs to be redone for 16 bit inte...Matt Ettus2010-03-251-0/+16
* invert the pushbuttons since they are active lowMatt Ettus2010-02-251-2/+2
* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-251-1/+2
* GPIOs now on the wishbone interfaceMatt Ettus2010-02-221-2/+4
* added gpio control to the wishboneMatt Ettus2010-02-181-1/+1
* Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-181-2/+10
* first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-161-25/+8
* copied over from safe_u1eMatt Ettus2010-02-161-0/+41