| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | watch the ethernet chip select on our debug bus | Matt Ettus | 2010-09-23 | 1 | -3/+4 |
| * | fix timing issue on DAC outputs with rev 2. This puts the whole system on a ... | Matt Ettus | 2010-09-21 | 1 | -31/+6 |
| * | updated pins to match rev2, removed dip switch, etc. seems to compile ok. | Matt Ettus | 2010-09-09 | 1 | -4/+4 |
| * | delay the q channel to make the channels line up on the AD9862 | Matt Ettus | 2010-08-17 | 1 | -1/+6 |
| * | use DDR regs instead of a 2nd clock | Matt Ettus | 2010-06-01 | 1 | -8/+46 |
| * | vita49 tx and rx added in, all sample rates now at main system clock rate. | Matt Ettus | 2010-06-01 | 1 | -7/+61 |
| * | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 1 | -0/+4 |
| * | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 1 | -0/+7 |
| * | added pps and time capability | Matt Ettus | 2010-04-15 | 1 | -2/+4 |
| * | connect 2 clock gen controls and 3 status pins to the wishbone so they can be... | Matt Ettus | 2010-03-26 | 1 | -0/+4 |
| * | connected spi pins, but the spi core still needs to be redone for 16 bit inte... | Matt Ettus | 2010-03-25 | 1 | -0/+16 |
| * | invert the pushbuttons since they are active low | Matt Ettus | 2010-02-25 | 1 | -2/+2 |
| * | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 1 | -1/+2 |
| * | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 1 | -2/+4 |
| * | added gpio control to the wishbone | Matt Ettus | 2010-02-18 | 1 | -1/+1 |
| * | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 1 | -2/+10 |
| * | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 1 | -25/+8 |
| * | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 1 | -0/+41 |
