| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | connect 2 clock gen controls and 3 status pins to the wishbone so they can ↵ | Matt Ettus | 2010-03-26 | 1 | -5/+5 |
| | | | | | be read/controlled from SW | ||||
| * | connected spi pins, but the spi core still needs to be redone for 16 bit ↵ | Matt Ettus | 2010-03-25 | 1 | -33/+39 |
| | | | | | | | interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs | ||||
| * | GPIOs now on the wishbone interface | Matt Ettus | 2010-02-22 | 1 | -32/+32 |
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| * | Added I2C, UART, debug pins, misc wishbone stuff | Matt Ettus | 2010-02-18 | 1 | -19/+19 |
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| * | first cut at gpmc <-> wb bridge, split u1e into core, top, and tb | Matt Ettus | 2010-02-16 | 1 | -8/+6 |
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| * | copied over from safe_u1e | Matt Ettus | 2010-02-16 | 1 | -0/+262 |
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