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path: root/usrp2/top/u1e/Makefile
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* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-206/+39
* use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-011-1/+1
* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-011-0/+5
* combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-201-0/+1
* moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-121-0/+4
* add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-041-0/+1
* find time_64bitMatt Ettus2010-04-201-0/+1
* async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-151-3/+3
* handle all tri-state in the top level of gpmcMatt Ettus2010-04-151-0/+2
* more progress on synchronous interfaceMatt Ettus2010-04-141-0/+1
* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-1/+1
* minor changes to get it to synthesizeMatt Ettus2010-04-131-0/+3
* added 16-bit wide atr controllerMatt Ettus2010-04-011-1/+1
* connect up the 16 bit spi coreMatt Ettus2010-03-261-2/+1
* point to the new filesMatt Ettus2010-02-251-0/+2
* first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-0/+1
* settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-221-1/+1
* GPIOs now on the wishbone interfaceMatt Ettus2010-02-221-1/+1
* first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-161-1/+2
* copied over from safe_u1eMatt Ettus2010-02-161-0/+246