aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/sdr_lib
Commit message (Collapse)AuthorAgeFilesLines
* dsp: clear cic_decim when not enabledMatt Ettus2011-08-151-4/+4
|
* dsp: allow tx iq balance to be removed at compile timeMatt Ettus2011-07-281-23/+38
|
* dsp: option to remove iq compensation at compile timeMatt Ettus2011-07-281-35/+40
|
* dsp: reduce bitwidth to help timingMatt Ettus2011-07-191-4/+6
|
* dsp: reset the interpolator when the rate changes, to prevent oscillationMatt Ettus2011-07-191-7/+8
|
* u1p/u1e: cleanup some warnings, connect the correct clocksMatt Ettus2011-06-161-1/+1
|
* u1e-dsp: attach tx dc offset and iq balanceMatt Ettus2011-06-141-4/+5
|
* dsp: implement iqbal on txMatt Ettus2011-06-122-30/+35
|
* dsp: remove unused setting regMatt Ettus2011-06-081-4/+0
|
* dsp: added tx_frontend, instantiated in u2/u2pMatt Ettus2011-06-083-19/+59
|
* dsp: small_hb_dec now 24 bits wide as wellMatt Ettus2011-06-082-39/+38
|
* dsp: do everything at 24 bits wideMatt Ettus2011-06-085-120/+204
|
* dsp: pass 24 bit wide signals between frontend and dsp core.Matt Ettus2011-06-082-8/+12
| | | | Overkill, but we have the bits already, so why throw them away?
* dsp: clip in hb_dec to prevent the rare overflow with certain frequencies at ↵Matt Ettus2011-06-082-6/+19
| | | | max amplitude
* dsp: add guard bit to top of cordic to allow clipping on output instead of ↵Matt Ettus2011-06-081-5/+9
| | | | wrapping
* dsp: fix off-by-one error in timing of hb_decMatt Ettus2011-06-081-1/+1
|
* dsp: register hb outputMatt Ettus2011-06-084-293/+15
|
* dsp: no need to keep all the low order bits from the accumulatorMatt Ettus2011-06-081-2/+2
|
* dsp: increase gain of small_hb_dec because it used to scale down by factor ↵Matt Ettus2011-06-082-5/+9
| | | | of 2. Clip if needed.
* dsp: use round_sd in small_hb_decMatt Ettus2011-06-081-3/+6
|
* dsp: reorganized scaling and rounding, removed multipliers (will put back in ↵Matt Ettus2011-06-083-49/+46
| | | | a different location)
* dsp: testbenches for dsp blocksMatt Ettus2011-06-082-0/+113
|
* dsp: tx_dcoffset, not integrated yetMatt Ettus2011-06-081-0/+26
|
* dsp: add resets for simulation purposesMatt Ettus2011-06-081-4/+4
|
* dsp: do proper rounding at the end of dsp chainMatt Ettus2011-06-081-1/+1
|
* dsp: reworked muxes on rxMatt Ettus2011-06-082-22/+31
|
* dsp: more typosMatt Ettus2011-06-081-2/+2
|
* dsp: new files in dsp directoryMatt Ettus2011-06-081-0/+3
|
* dsp: fix typosMatt Ettus2011-06-083-14/+14
|
* dsp: add2_and_clip_reg and round_sd now are now strobed to be compatibleMatt Ettus2011-06-086-26/+46
| | | | with strobed (non-full rate) data
* u2/u2p: use new rx_frontend in u2 and u2pMatt Ettus2011-06-081-2/+2
|
* dsp: use sigma delta rounding in rx_dcoffset and in dsp_core_rxMatt Ettus2011-06-082-16/+6
|
* dsp: reworked round_sd, it is much simpler nowMatt Ettus2011-06-082-34/+14
|
* dsp: first cut at sigma-delta roundingMatt Ettus2011-06-082-0/+92
|
* dsp: pass the error through in the rounding functionMatt Ettus2011-06-081-4/+9
|
* u2/u2p: misc connection and compilation fixesMatt Ettus2011-06-083-18/+20
|
* unused netsMatt Ettus2011-06-081-1/+0
|
* u2/u2p: pull IQ balance and dcoffset out of dsp_core, put in frontend moduleMatt Ettus2011-06-083-42/+78
|
* redone DC offset with sigma-delta quantizationMatt Ettus2011-06-085-27/+80
|
* added copyrightsJosh Blum2011-06-0738-0/+646
|
* clean up a bunch of warnings and incorrect bus widthsMatt Ettus2011-03-161-21/+5
|
* Clean up iq swapping on RX. It is now swapped in the top level.Matt Ettus2010-08-251-22/+13
| | | | widened muxes to 4 bits to match tx side and handle more ADCs in future
* remove warningsMatt Ettus2010-07-161-2/+2
|
* first attempt at cleaning up the build systemMatt Ettus2010-06-103-8/+228
|
* from UDP branch, changed names because I want these separate from the ↵Matt Ettus2010-05-271-0/+183
| | | | non-udp versions
* Merge branch 'udp' into master_merge_take2Matt Ettus2010-05-271-6/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
| * Merge branch 'corgan_fixes' into udp_corganMatt Ettus2010-04-262-27/+31
| |\ | |/ |/|
| * moved into subdirJosh Blum2010-01-2264-0/+5130
|
* Remove some warnings in dsp_core_rxJohnathan Corgan2010-02-231-3/+7
|
* Change bit width of CORDIC constants to remove meaningless warningJohnathan Corgan2010-02-231-24/+24
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 19:16:29 +0000