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added stack start signal to zpu
removed wb perifs in n210 out of 0-16k
added reset controller for main app
rewire cpu addr line after booted use 0-16k
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and u2p
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* u1e: (130 commits)
invert led signals because they are active low
duh
allow for CS to rise before, at the same time, or after OE
better debug pins
watch the ethernet chip select on our debug bus
fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift
send all gpmc signals to mictor
updated pins to match rev2, removed dip switch, etc. seems to compile ok.
pins are different on rev2
fixed makefile to compile with our new system
add register to tell host about compatibility level and which image we are using
move declaration to make loopback compile
no need for protocol headers since we're not doing ethernet
match the signal names in this design
debug pins cleanup
properly integrate the new tx chain
catch up with tx_policy
attach run_tx and run_rx to leds
connect atr
delay the q channel to make the channels line up on the AD9862
...
Conflicts:
usrp2/control_lib/Makefile.srcs
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Made so Makefile changes as well to get it to build
* master:
new make works on ise12
produces good bin files
first attempt at cleaning up the build system
get rid of debug stuff to help timing
move u2_core into u2_rev3 directory to simplify directory structure and save headaches
Conflicts:
usrp2/fifo/fifo36_to_fifo18.v
usrp2/top/u2_rev3/Makefile
usrp2/top/u2_rev3/Makefile.udp
usrp2/top/u2_rev3/u2_core_udp.v
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* ise12_exp:
zero out debug pins. helps timing a little bit.
non-udp uses a different address for the tx dsp core
manual merge to use localparams from udp version
from UDP branch, changed names because I want these separate from the non-udp versions
ignore output files
new files from udp branch added to main Makefile
change the debug pins, which makes it more reliable. This is unnerving.
experimental mods to make ram loader fully synchronous. Based on IJB's work
fixes from IJB from 5/24. Basically connect unconnected wires.
removes the icache and pipelines the reads
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* master:
get rid of some warnings by declaring setting reg width
added width parameter to avoid warnings (thanks IJB) and default value parameter
added pragmas suggested by Ian Buckley to help ISE12 synthesis
get rid of old CVS linkage
settings bus to dsp_clk now uses clock crossing fifo
remove files for old prototypes, they were confusing people
revert commit 9899b81f920 which should have improved timing but didn't
Conflicts:
usrp2/control_lib/setting_reg.v
usrp2/top/u2_core/u2_core.v
usrp2/top/u2_rev3/Makefile
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get rid of asynchronous resets
fix spelling error
corrected comment
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seem to work ok
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