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* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-0/+27
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Made so Makefile changes as well to get it to build * master: new make works on ise12 produces good bin files first attempt at cleaning up the build system get rid of debug stuff to help timing move u2_core into u2_rev3 directory to simplify directory structure and save headaches Conflicts: usrp2/fifo/fifo36_to_fifo18.v usrp2/top/u2_rev3/Makefile usrp2/top/u2_rev3/Makefile.udp usrp2/top/u2_rev3/u2_core_udp.v
| * first attempt at cleaning up the build systemMatt Ettus2010-06-101-0/+28
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* | Merge branch 'ise12_exp' into u1eMatt Ettus2010-06-012-11/+21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12_exp: zero out debug pins. helps timing a little bit. non-udp uses a different address for the tx dsp core manual merge to use localparams from udp version from UDP branch, changed names because I want these separate from the non-udp versions ignore output files new files from udp branch added to main Makefile change the debug pins, which makes it more reliable. This is unnerving. experimental mods to make ram loader fully synchronous. Based on IJB's work fixes from IJB from 5/24. Basically connect unconnected wires. removes the icache and pipelines the reads
| * | removes the icache and pipelines the readsMatt Ettus2010-05-202-11/+21
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* | Merge branch 'master' into u1e_merge_with_masterMatt Ettus2010-05-27222-318/+6
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master: get rid of some warnings by declaring setting reg width added width parameter to avoid warnings (thanks IJB) and default value parameter added pragmas suggested by Ian Buckley to help ISE12 synthesis get rid of old CVS linkage settings bus to dsp_clk now uses clock crossing fifo remove files for old prototypes, they were confusing people revert commit 9899b81f920 which should have improved timing but didn't Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
| * added pragmas suggested by Ian Buckley to help ISE12 synthesisMatt Ettus2010-05-181-3/+6
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| * get rid of old CVS linkageMatt Ettus2010-05-18221-315/+0
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* | 16 bit wide spi coreMatt Ettus2010-03-271-0/+182
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* | remove timescale junkMatt Ettus2010-03-265-21/+19
| | | | | | | | | | | | | | | | get rid of asynchronous resets fix spelling error corrected comment
* | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
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* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22331-0/+1515024