| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | async seems to work with packet lengths now. Still need to do wishbone regs ... | Matt Ettus | 2010-04-15 | 1 | -12/+34 |
| * | change time parameters because Xilinx IP has a 1ps timescale | Matt Ettus | 2010-04-15 | 1 | -14/+27 |
| * | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 2 | -2/+99 |
| * | lengthened delay between cycles, added more transactions on the data bus | Matt Ettus | 2010-04-12 | 1 | -2/+7 |
| * | loopback and test | Matt Ettus | 2010-02-25 | 1 | -5/+6 |
| * | First cut at passing data buffers around on GPMC bus | Matt Ettus | 2010-02-25 | 1 | -4/+19 |
| * | speed up the presentation of registered wb data to the gpmc | Matt Ettus | 2010-02-17 | 1 | -11/+15 |
| * | wishbone bridge now with minimal functionality. Need to check | Matt Ettus | 2010-02-16 | 1 | -0/+70 |
| * | Moved usrp2 fpga files into usrp2 subdir. | Josh Blum | 2010-01-22 | 20 | -0/+8493 |
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