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* fpga: xclock fix for edge case conditionJosh Blum2012-05-081-6/+8
* e100: squashed work on bus implementation on GPMCJosh Blum2011-08-2919-942/+521
* added copyrightsJosh Blum2011-06-0711-0/+187
* fifo36_mux now has shortfifos on the input ports as well as outputMatt Ettus2011-02-252-6/+3
* timed tester : Bring out src/dst flags for rx chain for testing.Philip Balister2011-02-251-1/+11
* u1e: hook up tester controlsMatt Ettus2011-02-171-5/+7
* move declarations to before useMatt Ettus2011-02-161-8/+8
* hook up under/overruns for debug purposesMatt Ettus2011-02-161-5/+5
* e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-161-5/+89
* allow for CS to rise before, at the same time, or after OEMatt Ettus2010-09-241-7/+6
* added ability to clear out fifos of tx and rx.Matt Ettus2010-06-172-16/+16
* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-0/+20
* debug pinsMatt Ettus2010-06-082-3/+8
* added little endian capability for gpmc to fifo and fifo to gpmc, since ARM i...Matt Ettus2010-06-062-4/+4
* get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bitMatt Ettus2010-06-062-4/+6
* moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-121-38/+53
* have_space and have_packet now stay high even while busy,Matt Ettus2010-05-033-4/+6
* Only allow new packets if we can fit the largest possible packet (2KB)Matt Ettus2010-04-231-1/+1
* Register outputs to omap to prevent runt pulses from falsely triggering inter...Matt Ettus2010-04-233-7/+20
* access frame length regs from wishboneMatt Ettus2010-04-151-4/+4
* async seems to work with packet lengths now. Still need to do wishbone regs ...Matt Ettus2010-04-153-22/+35
* async gpmc progressMatt Ettus2010-04-152-0/+153
* add bus error reportingMatt Ettus2010-04-151-3/+9
* correct name of moduleMatt Ettus2010-04-151-2/+2
* progress on synchronous gpmc, but it may not be possible due to the limited n...Matt Ettus2010-04-153-43/+45
* handle all tri-state in the top level of gpmcMatt Ettus2010-04-152-6/+6
* more sync progress. This is just a skeleton for now, with junk contentMatt Ettus2010-04-141-0/+56
* more progress on synchronous interfaceMatt Ettus2010-04-143-26/+94
* renamed to async. Will be building a sync version for GPMC_CLKMatt Ettus2010-04-141-2/+2
* make timing diagrams for bus transactions. Still need to do readsMatt Ettus2010-04-145-0/+46
* probably won't be using this, and it hasn't been testedMatt Ettus2010-04-141-0/+46
* minor changes to get it to synthesizeMatt Ettus2010-04-131-1/+1
* replaced ram interface with a fifo interface. still need to do rx sideMatt Ettus2010-04-122-81/+110
* split out gpmc to wishbone interface to make gpmc top level cleanerMatt Ettus2010-04-121-0/+57
* gpmc debug pinsMatt Ettus2010-02-251-1/+8
* fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
* corrected logicMatt Ettus2010-02-251-17/+7
* edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
* First cut at passing data buffers around on GPMC busMatt Ettus2010-02-252-11/+122
* first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-231-6/+18
* speed up the presentation of registered wb data to the gpmcMatt Ettus2010-02-171-2/+5
* wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-161-2/+2
* first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-161-0/+66
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