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* dsp rework: pass vita clears into dsp modules, unified fifo clearsJosh Blum2012-02-042-2/+2
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* b100: connect all clears for gpifJosh Blum2012-02-032-14/+7
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* Slave FIFO: fix for PKTEND not asserting @ end of RX.Nick Foster2012-01-121-8/+8
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* B100: moar buffering on TX for better performance in bidirectional applicationsNick Foster2012-01-121-3/+3
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* Squashed slave mode changes onto master.Nick Foster2012-01-123-15/+482
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* b100: fix warnings, complete removal of test codeMatt Ettus2011-11-041-0/+3
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* b100: remove test features from GPIF to save spaceMatt Ettus2011-11-042-82/+9
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* added copyrightsJosh Blum2011-06-078-0/+136
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* B100: added some packet splitter debug pins, removed debug from GPIO port, ↵Nick Foster2011-05-263-10/+18
| | | | swapped I&Q in interleaver
* u1p: reset gpifMatt Ettus2011-05-261-2/+2
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* u1p: connect frames per packetMatt Ettus2011-05-261-1/+1
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* u1p: implement a signal to indicate a partially full usb lut, to flush itMatt Ettus2011-05-265-18/+166
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* u1p: vita packet generator for testing purposesMatt Ettus2011-05-261-3/+3
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* should split and reframe packets properlyMatt Ettus2011-05-262-27/+58
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* u1p: do padding outside of gpif_rd, in packet_splitterMatt Ettus2011-05-265-14/+188
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* u1p: add new file to buildMatt Ettus2011-05-261-0/+1
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* u1p: debug pinsMatt Ettus2011-05-261-1/+3
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* u1p: better way of reframing the packetsMatt Ettus2011-05-263-5/+83
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* u1p:wr testbenchMatt Ettus2011-05-261-0/+86
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* u1p: use 18 bit fifos and use full size of a block ram in the tx pathMatt Ettus2011-05-261-6/+7
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* u1p: gpif-to-fx2 path should now handle arbitrary sized packets, up to 2KBMatt Ettus2011-05-261-22/+29
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* u1p: pass tx status/error packets back through GPIF over the response ↵Matt Ettus2011-05-261-5/+21
| | | | channel (short packets)
* u1p: added loopback and timed capability just like u1eMatt Ettus2011-05-261-19/+91
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* u1p: fix bus widths and other warningsMatt Ettus2011-05-263-32/+32
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* u1p: add clear ports to gpif, not hooked up yetMatt Ettus2011-05-261-1/+1
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* add padding into gpif response pathMatt Ettus2011-05-261-3/+8
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* fifo to wb should be functionally complete, needs testingMatt Ettus2011-05-262-13/+9
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* not usedMatt Ettus2011-05-261-16/+0
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* fix ctrl/resp path to pass all 16 bits of data instead of the bottom bitMatt Ettus2011-05-263-38/+47
| | | | | typos fixed, everything is connected now, should just have off-by-1 error lots of debug pins added
* first steps to a command packet handler for u1+Matt Ettus2011-05-262-0/+17
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* redone gpif interface to match nick's new specMatt Ettus2011-05-263-60/+123
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* hook up flow control pinsMatt Ettus2011-05-261-2/+10
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* added a loopback control port, will do full wishbone interface laterMatt Ettus2011-05-261-1/+8
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* progress on gpif interfaceMatt Ettus2011-05-263-101/+118
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* gpif skeletonsMatt Ettus2011-05-264-0/+80
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* skeletonMatt Ettus2011-05-261-0/+122