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* added copyrightsJosh Blum2011-06-071-0/+17
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* B100: added some packet splitter debug pins, removed debug from GPIO port, ↵Nick Foster2011-05-261-8/+11
| | | | swapped I&Q in interleaver
* u1p: connect frames per packetMatt Ettus2011-05-261-1/+1
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* u1p: implement a signal to indicate a partially full usb lut, to flush itMatt Ettus2011-05-261-3/+4
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* u1p: vita packet generator for testing purposesMatt Ettus2011-05-261-3/+3
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* u1p: do padding outside of gpif_rd, in packet_splitterMatt Ettus2011-05-261-4/+9
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* u1p: debug pinsMatt Ettus2011-05-261-1/+3
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* u1p: better way of reframing the packetsMatt Ettus2011-05-261-1/+10
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* u1p: pass tx status/error packets back through GPIF over the response ↵Matt Ettus2011-05-261-5/+21
| | | | channel (short packets)
* u1p: added loopback and timed capability just like u1eMatt Ettus2011-05-261-19/+91
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* u1p: fix bus widths and other warningsMatt Ettus2011-05-261-15/+15
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* u1p: add clear ports to gpif, not hooked up yetMatt Ettus2011-05-261-1/+1
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* add padding into gpif response pathMatt Ettus2011-05-261-3/+8
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* fifo to wb should be functionally complete, needs testingMatt Ettus2011-05-261-12/+9
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* fix ctrl/resp path to pass all 16 bits of data instead of the bottom bitMatt Ettus2011-05-261-25/+33
| | | | | typos fixed, everything is connected now, should just have off-by-1 error lots of debug pins added
* redone gpif interface to match nick's new specMatt Ettus2011-05-261-40/+38
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* hook up flow control pinsMatt Ettus2011-05-261-2/+10
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* added a loopback control port, will do full wishbone interface laterMatt Ettus2011-05-261-1/+8
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* progress on gpif interfaceMatt Ettus2011-05-261-90/+61
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* gpif skeletonsMatt Ettus2011-05-261-0/+16
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* skeletonMatt Ettus2011-05-261-0/+122