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* u1e: new 2 clock fifo, 18 bits by 1KMatt Ettus2011-06-121-0/+5
* added copyrightsJosh Blum2011-06-0737-0/+629
* u2p-rebase: go back to versions on nextMatt Ettus2011-05-261-2/+1
* u1p: use 18 bit fifos and use full size of a block ram in the tx pathMatt Ettus2011-05-261-7/+12
* u1p: pass tx status/error packets back through GPIF over the response channel...Matt Ettus2011-05-263-1/+80
* add padding into gpif response pathMatt Ettus2011-05-261-0/+1
* pad out packets to a minimum lengthMatt Ettus2011-05-261-0/+66
* u1e: get dsp_framer36 from u1p so it can skip the protocol headerMatt Ettus2011-05-091-6/+10
* udp: short fifos on prot_eng in and outMatt Ettus2011-03-161-16/+2
* u1e: keep up with fixes made for u2/u2p, make it compile againMatt Ettus2011-03-151-15/+8
* packet_router: created packet dispatcher component to replace packet inspecto...Josh Blum2011-03-083-236/+293
* first cut at 36:72 and 72:36 for extra wide fifos. untestedMatt Ettus2011-03-072-0/+188
* u2/u2p: proper connections for dsp_framerMatt Ettus2011-03-071-1/+0
* u2/u2p: fix off-by-one error in dsp_framerMatt Ettus2011-03-061-1/+2
* u2/u2p: removed redundant shortfifos from udp path (they are in the size adap...Matt Ettus2011-03-051-17/+5
* u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-051-23/+5
* u2/u2p: rework ports againMatt Ettus2011-03-041-3/+3
* u2/u2p: reworked port names on packet_routerMatt Ettus2011-03-041-3/+3
* u2/u2p: reworked dsp framer to work more like a fifo, and do vita length corr...Matt Ettus2011-03-041-87/+56
* u2/u2p: allow cpu to receive or send packets longer than the buffer size.Matt Ettus2011-03-041-7/+10
* make fifo36_to_ll8 properly handle partial end lines.Matt Ettus2011-03-042-152/+31
* Merge branch 'gpmc_testing' into ethfifo_reorgMatt Ettus2011-03-039-12/+307
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| * timed packet generator : Temporarily use a checksum rather than a crc to vali...Philip Balister2011-02-261-3/+9
| * correct port namesMatt Ettus2011-02-251-2/+2
| * fifo36_mux now has shortfifos on the input ports as well as outputMatt Ettus2011-02-251-12/+25
| * e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-163-2/+22
| * Fix endianess for packet length and sequence number for e100 timed image.Philip Balister2011-02-161-8/+8
| * put these files in the right place. newfifo is long gone.Matt Ettus2011-02-168-0/+256
* | all: removed old unused fifosMatt Ettus2011-03-032-21/+1
* | all: short fifos on front and back of fifo36_to_fifo19Matt Ettus2011-03-031-15/+33
* | u2/u2p: shortfifos in fifo36_to_ll8, no more _n junkMatt Ettus2011-03-031-28/+43
* | u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdspMatt Ettus2011-03-031-7/+10
* | u2/u2p: switch over to 36 bit wide ethernet wrapperMatt Ettus2011-03-031-27/+47
* | ethfifo_reorg: switch buffer int2 lastline to work as a length parameterJosh Blum2011-03-031-5/+6
* | u2/u2p: get rid of redeclarationMatt Ettus2011-03-031-1/+0
* | u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapperMatt Ettus2011-03-031-8/+6
* | u2/u2p: short fifos put on both sides of ll8_to_fifo19Matt Ettus2011-03-031-27/+44
* | u2/u2p: inserted short fifo into the packet inspector path to help routing an...Matt Ettus2011-02-171-1/+13
* | added port_sel param to dsp framerJosh Blum2011-02-172-4/+5
* | packet_router: added support for two dsps into routerJosh Blum2011-02-151-14/+20
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* believed to fix fifo swizzling with partially empty linesMatt Ettus2011-01-213-25/+114
* xbar and valve: fix switching delayed by active signalJosh Blum2011-01-112-9/+12
* packet_router: tweak mode SR (its only 1 bit)Josh Blum2011-01-071-3/+2
* usrp2: removed unused changed signal for mode selectionJosh Blum2010-12-291-2/+1
* packet_router: replace buffers interfaced in packet router with buffer_int2Josh Blum2010-12-283-163/+25
* now uses 2 rams, one for read, one for writeMatt Ettus2010-12-281-89/+97
* reformattingMatt Ettus2010-12-281-5/+1
* first cut at new buffer interface for CPU. Like old buffer_int plusMatt Ettus2010-12-281-0/+169
* unused lineMatt Ettus2010-12-281-1/+0
* packet_router: use the mode register to reset hs control and cpu smsJosh Blum2010-12-271-22/+13
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