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* add a fifo to the end of the mux to help in timing.Matt Ettus2010-10-081-6/+13
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* revert unneeded changes and incorrect commentsMatt Ettus2010-10-071-4/+4
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* Matt's attempt at mergingMatt Ettus2010-08-163-5510/+23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'tx_policy' into ise12_efifo_work * tx_policy: rx error context packets should not be marked as errors in the fifo provide a way to get out of the error state without processor intervention sequence number reset upon programming streamid attempt at avoiding infinite error messages implemented "next packet" and "next burst" policies sequence errors can happen on start of burst as well. more informative error codes cleaner error handling introduce new error types test mux and gen_context_pkt this is an output file, it shouldn't be checked in insert protocol engine flags when requested move the streamid so it isn't at the same address as clear_state connect the demux fix a typo tx error packets now muxed into the ethernet stream back to the host checkpoint. New context packet generator to report underruns and other errors Conflicts: usrp2/top/u2_rev3/u2_core_udp.v
| * test mux and gen_context_pktMatt Ettus2010-07-281-3/+22
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| * this is an output file, it shouldn't be checked inMatt Ettus2010-07-281-5506/+0
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| * move the streamid so it isn't at the same address as clear_stateMatt Ettus2010-07-281-1/+1
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* | Merge branch 'ise12' into ise12_efifo_workMatt Ettus2010-08-163-0/+109
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet fix to stop endless error packets updated tests to match new features error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets reload bit for vita rx ctrl
| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
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| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
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| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
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* | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵Ian Buckley2010-07-311-4/+4
| | | | | | | | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched.
* | moved forward from the old branchMatt Ettus2010-07-142-4/+30
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* first attempt at cleaning up the build systemMatt Ettus2010-06-1022-0/+7551
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