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* u2/u2p: fix off-by-one error in dsp_framerMatt Ettus2011-03-061-1/+2
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* u2/u2p: removed redundant shortfifos from udp path (they are in the size ↵Matt Ettus2011-03-051-17/+5
| | | | adapters now)
* u2/u2p: moved dsp framer into vita_rx_chainMatt Ettus2011-03-051-23/+5
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* u2/u2p: rework ports againMatt Ettus2011-03-041-3/+3
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* u2/u2p: reworked port names on packet_routerMatt Ettus2011-03-041-3/+3
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* u2/u2p: reworked dsp framer to work more like a fifo, and do vita length ↵Matt Ettus2011-03-041-87/+56
| | | | correction
* u2/u2p: allow cpu to receive or send packets longer than the buffer size.Matt Ettus2011-03-041-7/+10
| | | | on reception, the rest is dropped. On sending, the rest is a repeat of the buffer.
* make fifo36_to_ll8 properly handle partial end lines.Matt Ettus2011-03-042-152/+31
| | | | I could swear I've fixed this before...
* Merge branch 'gpmc_testing' into ethfifo_reorgMatt Ettus2011-03-039-12/+307
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | * gpmc_testing: timed packet generator : Temporarily use a checksum rather than a crc to validate packet integrity. correct port names fifo36_mux now has shortfifos on the input ports as well as output timed tester : Bring out src/dst flags for rx chain for testing. u1e: hook up tester controls move declarations to before use hook up under/overruns for debug purposes e100: integrate loopback and timed testing into main image Fix endianess for packet length and sequence number for e100 timed image. put these files in the right place. newfifo is long gone.
| * timed packet generator : Temporarily use a checksum rather than a crc to ↵Philip Balister2011-02-261-3/+9
| | | | | | | | validate packet integrity.
| * correct port namesMatt Ettus2011-02-251-2/+2
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| * fifo36_mux now has shortfifos on the input ports as well as outputMatt Ettus2011-02-251-12/+25
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| * e100: integrate loopback and timed testing into main imageMatt Ettus2011-02-163-2/+22
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| * Fix endianess for packet length and sequence number for e100 timed image.Philip Balister2011-02-161-8/+8
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| * put these files in the right place. newfifo is long gone.Matt Ettus2011-02-168-0/+256
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* | all: removed old unused fifosMatt Ettus2011-03-032-21/+1
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* | all: short fifos on front and back of fifo36_to_fifo19Matt Ettus2011-03-031-15/+33
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* | u2/u2p: shortfifos in fifo36_to_ll8, no more _n junkMatt Ettus2011-03-031-28/+43
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* | u2/u2p: rxdsp/cpu/err muxing now prioritizes cpu and err over rxdspMatt Ettus2011-03-031-7/+10
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* | u2/u2p: switch over to 36 bit wide ethernet wrapperMatt Ettus2011-03-031-27/+47
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* | ethfifo_reorg: switch buffer int2 lastline to work as a length parameterJosh Blum2011-03-031-5/+6
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* | u2/u2p: get rid of redeclarationMatt Ettus2011-03-031-1/+0
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* | u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapperMatt Ettus2011-03-031-8/+6
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* | u2/u2p: short fifos put on both sides of ll8_to_fifo19Matt Ettus2011-03-031-27/+44
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* | u2/u2p: inserted short fifo into the packet inspector path to help routing ↵Matt Ettus2011-02-171-1/+13
| | | | | | | | and timing
* | added port_sel param to dsp framerJosh Blum2011-02-172-4/+5
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* | packet_router: added support for two dsps into routerJosh Blum2011-02-151-14/+20
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* believed to fix fifo swizzling with partially empty linesMatt Ettus2011-01-213-25/+114
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* xbar and valve: fix switching delayed by active signalJosh Blum2011-01-112-9/+12
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* packet_router: tweak mode SR (its only 1 bit)Josh Blum2011-01-071-3/+2
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* usrp2: removed unused changed signal for mode selectionJosh Blum2010-12-291-2/+1
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* packet_router: replace buffers interfaced in packet router with buffer_int2Josh Blum2010-12-283-163/+25
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* now uses 2 rams, one for read, one for writeMatt Ettus2010-12-281-89/+97
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* reformattingMatt Ettus2010-12-281-5/+1
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* first cut at new buffer interface for CPU. Like old buffer_int plusMatt Ettus2010-12-281-0/+169
| | | | a single buffer.
* unused lineMatt Ettus2010-12-281-1/+0
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* packet_router: use the mode register to reset hs control and cpu smsJosh Blum2010-12-271-22/+13
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* packet_router: all non ip/udp should also go to bothJosh Blum2010-12-131-7/+5
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* packet_router: harmless logic tweaksJosh Blum2010-12-122-11/+8
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* packet_router: reverted enable change to dsp framer, it was already correctJosh Blum2010-12-121-2/+1
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* packet_router: raise enable for bram reads the cycle before as wellJosh Blum2010-12-112-2/+4
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* packet_router: added fifo before cpu_out, tweaked inspection logicJosh Blum2010-12-101-25/+29
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* packet_router: gave the inspector a 4th output which is CPU onlyJosh Blum2010-12-101-83/+123
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* packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-0/+1
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* packet_router: split the control register into misc, cpu hs out, cpu hs inpJosh Blum2010-11-241-10/+24
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* packet_router: modification for sequence number and vrt header offsetJosh Blum2010-11-231-1/+1
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* packet_router: it makes more sense to connect the control flags this way nowJosh Blum2010-11-231-13/+6
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* packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-31/+33
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* packet_router: mux the crossbar input after the protocol framerJosh Blum2010-11-231-2/+12
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* packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-231-2/+42
| | | | udp_wrapper in top level with some fifo conversion stuff
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