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* packet_router: use the mode register to reset hs control and cpu smsJosh Blum2010-12-271-22/+13
* packet_router: all non ip/udp should also go to bothJosh Blum2010-12-131-7/+5
* packet_router: harmless logic tweaksJosh Blum2010-12-122-11/+8
* packet_router: reverted enable change to dsp framer, it was already correctJosh Blum2010-12-121-2/+1
* packet_router: raise enable for bram reads the cycle before as wellJosh Blum2010-12-112-2/+4
* packet_router: added fifo before cpu_out, tweaked inspection logicJosh Blum2010-12-101-25/+29
* packet_router: gave the inspector a 4th output which is CPU onlyJosh Blum2010-12-101-83/+123
* packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-0/+1
* packet_router: split the control register into misc, cpu hs out, cpu hs inpJosh Blum2010-11-241-10/+24
* packet_router: modification for sequence number and vrt header offsetJosh Blum2010-11-231-1/+1
* packet_router: it makes more sense to connect the control flags this way nowJosh Blum2010-11-231-13/+6
* packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-31/+33
* packet_router: mux the crossbar input after the protocol framerJosh Blum2010-11-231-2/+12
* packet_router: moved udp tx proto machine into packet router, replaced udp_wr...Josh Blum2010-11-231-2/+42
* packet_router: moved dsp framer into a module, added clr to splitter and renamedJosh Blum2010-11-234-93/+110
* packet_router: implemented crossbar and valve module, moved sreg into router ...Josh Blum2010-11-232-45/+65
* packet valve. will drop incoming data if shut off.Matt Ettus2010-11-231-0/+28
* abstract out the crossbar functionalityMatt Ettus2010-11-231-0/+40
* packet_router: transplanted the async error interface, its now sent into the ...Josh Blum2010-11-231-7/+16
* packet_router: added a way to program in the ip and mac addrs, and added insp...Josh Blum2010-11-231-2/+17
* packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-9/+41
* packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-12/+22
* packet_router: added splitter and mux for slow path stuff (also fixed typo in...Josh Blum2010-11-232-10/+95
* packet_router: renamed inspector output signals and connected (for now) to cp...Josh Blum2010-11-232-22/+52
* packet_router: use BRAM enables to perform pipelined readsJosh Blum2010-11-231-26/+21
* packet_router: use control register bit for master mode flagJosh Blum2010-11-231-2/+1
* packet_router: swapped comm mux for a crossbar, serdes crossbar out now muxed...Josh Blum2010-11-231-27/+62
* packet_router: used registered valid signal for BRAM read cycle delayJosh Blum2010-11-231-16/+15
* packet_router: created dsp framer for rx pathJosh Blum2010-11-231-6/+100
* packet_router: added lines for com crossbar and com output muxJosh Blum2010-11-231-13/+35
* packet_router: collapsed inspector states, fixed terminology for cpu inp vs outJosh Blum2010-11-231-163/+161
* packet_router: some tweaks, dsp output routing seems to work but has wrong of...Josh Blum2010-11-231-4/+10
* packet_router: added all input/output signals to module, created the comm mux...Josh Blum2010-11-231-6/+19
* packet_router: created com signals (device IO lines that may be ethernet or s...Josh Blum2010-11-231-79/+100
* packet_router: created inspector and added dsp output (however inspection log...Josh Blum2010-11-231-4/+133
* packet_router: connected and created CPU read from interface (slow path in pl...Josh Blum2010-11-231-47/+153
* packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-232-0/+121
* add a fifo to the end of the mux to help in timing.Matt Ettus2010-11-111-6/+13
* moved forward from the old branchMatt Ettus2010-11-112-4/+30
* occ needs to be 2 bits wide on a 36 bit fifo interface.Matt Ettus2010-11-101-1/+2
* catch up with tx_policyMatt Ettus2010-08-193-5510/+23
* Merge branch 'ise12' into u1eMatt Ettus2010-07-193-0/+109
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| * add mux and demux to buildMatt Ettus2010-07-151-0/+2
| * mux multiple fifo streams into one. Allows priority or round robinMatt Ettus2010-07-151-0/+57
| * split fifo into 2 streams based on first line in each packetMatt Ettus2010-07-151-0/+50
* | Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-145-78/+49
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* first attempt at cleaning up the build systemMatt Ettus2010-06-1022-0/+7551