| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge branch 'ise12' into ise12_efifo_work | Matt Ettus | 2010-08-16 | 3 | -0/+109 |
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | * ise12: move declaration ahead of use put run_tx and run_rx on the displayed LEDs remove warnings add mux and demux to build mux multiple fifo streams into one. Allows priority or round robin split fifo into 2 streams based on first line in each packet fix to stop endless error packets updated tests to match new features error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets reload bit for vita rx ctrl | ||||
| | * | add mux and demux to build | Matt Ettus | 2010-07-15 | 1 | -0/+2 |
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| | * | mux multiple fifo streams into one. Allows priority or round robin | Matt Ettus | 2010-07-15 | 1 | -0/+57 |
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| | * | split fifo into 2 streams based on first line in each packet | Matt Ettus | 2010-07-15 | 1 | -0/+50 |
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| * | | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵ | Ian Buckley | 2010-07-31 | 1 | -4/+4 |
| | | | | | | | | | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. | ||||
| * | | moved forward from the old branch | Matt Ettus | 2010-07-14 | 2 | -4/+30 |
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| * | first attempt at cleaning up the build system | Matt Ettus | 2010-06-10 | 22 | -0/+7551 |
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| Ettus' UHD Repository |
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