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path: root/usrp2/fifo/packet_router.v
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* packet_router: harmless logic tweaksJosh Blum2010-12-121-6/+3
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* packet_router: raise enable for bram reads the cycle before as wellJosh Blum2010-12-111-1/+2
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* packet_router: added fifo before cpu_out, tweaked inspection logicJosh Blum2010-12-101-25/+29
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* packet_router: gave the inspector a 4th output which is CPU onlyJosh Blum2010-12-101-83/+123
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* packet_router: added status readback for mode, incremented compat numberJosh Blum2010-11-241-0/+1
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* packet_router: split the control register into misc, cpu hs out, cpu hs inpJosh Blum2010-11-241-10/+24
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* packet_router: modification for sequence number and vrt header offsetJosh Blum2010-11-231-1/+1
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* packet_router: it makes more sense to connect the control flags this way nowJosh Blum2010-11-231-13/+6
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* packet_router: program the dsp udp port and ip addr through setting registersJosh Blum2010-11-231-31/+33
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* packet_router: mux the crossbar input after the protocol framerJosh Blum2010-11-231-2/+12
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* packet_router: moved udp tx proto machine into packet router, replaced ↵Josh Blum2010-11-231-2/+42
| | | | udp_wrapper in top level with some fifo conversion stuff
* packet_router: moved dsp framer into a module, added clr to splitter and renamedJosh Blum2010-11-231-88/+6
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* packet_router: implemented crossbar and valve module, moved sreg into router ↵Josh Blum2010-11-231-45/+63
| | | | module
* packet_router: transplanted the async error interface, its now sent into the ↵Josh Blum2010-11-231-7/+16
| | | | packet router to be muxed to com out
* packet_router: added a way to program in the ip and mac addrs, and added ↵Josh Blum2010-11-231-2/+17
| | | | inspector check
* packet_router: fixed sof bug for cpu (== 1), some logic tweaks, added debugJosh Blum2010-11-231-9/+41
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* packet_router: registered control flags, added clear to all state machinesJosh Blum2010-11-231-12/+22
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* packet_router: added splitter and mux for slow path stuff (also fixed typo ↵Josh Blum2010-11-231-10/+27
| | | | in crossbar input)
* packet_router: renamed inspector output signals and connected (for now) to ↵Josh Blum2010-11-231-22/+51
| | | | cpu, dsp, crs
* packet_router: use BRAM enables to perform pipelined readsJosh Blum2010-11-231-26/+21
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* packet_router: use control register bit for master mode flagJosh Blum2010-11-231-2/+1
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* packet_router: swapped comm mux for a crossbar, serdes crossbar out now ↵Josh Blum2010-11-231-27/+62
| | | | muxed into the comm output
* packet_router: used registered valid signal for BRAM read cycle delayJosh Blum2010-11-231-16/+15
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* packet_router: created dsp framer for rx pathJosh Blum2010-11-231-6/+100
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* packet_router: added lines for com crossbar and com output muxJosh Blum2010-11-231-13/+35
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* packet_router: collapsed inspector states, fixed terminology for cpu inp vs outJosh Blum2010-11-231-163/+161
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* packet_router: some tweaks, dsp output routing seems to work but has wrong ↵Josh Blum2010-11-231-4/+10
| | | | offset
* packet_router: added all input/output signals to module, created the comm ↵Josh Blum2010-11-231-6/+19
| | | | muxes (in and out)
* packet_router: created com signals (device IO lines that may be ethernet or ↵Josh Blum2010-11-231-79/+100
| | | | serdes)
* packet_router: created inspector and added dsp output (however inspection ↵Josh Blum2010-11-231-4/+133
| | | | logic does not enable it yet)
* packet_router: connected and created CPU read from interface (slow path in ↵Josh Blum2010-11-231-47/+153
| | | | place)
* packet_router: created nearly empty router with eth in attached to mapped memoryJosh Blum2010-11-231-0/+120
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