| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | External FIFO tested in simulation and on USRP2 from decimation 64->8 with ↵ | Ian Buckley | 2010-07-31 | 9 | -79/+7073 |
| | | | | | | | | | current head UHD code. Apparently operation is "flawless" but more regression and corner case regression could and should be done. Tristate drivers have been added at the top level of the hierarchy for the SRAM databus as is considered good practice for both Xilinx and ASIC design flows and so both top level and core fils have been touched. | ||||
| * | Checkpoint checkin. | Ian Buckley | 2010-07-29 | 9 | -0/+1013 |
| | | | | | | Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes. Not clear if its a logic or AC timing/SI issue yet. | ||||
| * | get it to build | Matt Ettus | 2010-07-14 | 4 | -5/+8 |
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| * | moved forward from the old branch | Matt Ettus | 2010-07-14 | 6 | -0/+846 |
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index : uhd | |
| Ettus' UHD Repository |
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